Dear Team,
I asked a related question earlier.(https://forum.allaboutcircuits.com/...summing-amplifier-design.179335/#post-1633714).
Below is my requirement.

I have a DC voltage(VDD) which varies from 1.6V to 3.6V. I CLK signal [0 to 5V,1Mhz] is used to vary this VDD in such a way that when CLK is LOW the circuit output is VDD/2 and when it is High circuit output should be VDD. For example, Let us say VDD=2V, then for LOW CLK the output should be 1V and HIGH CLK output should be 2V.

The issue I am facing now is, When the buffer is not connected to the switch the output of the buffer is proper VDD/2, but once it is connected to the switch the output of the buffer is spiky.

May i know how to solve this issue







Regards
HARI

 

hi hoy,
Please post your LTS asc file and the analog switch model.
E

 

Hi Eric,
I am not able to upload the .asc file.I did not see any option for that.If yoy know the same please let me know.
The switch is ADG719 from Analog devices.
Regards
HAri

 

hi h,
What I use to upload asc files is to add an extra .txt to the name.

eg: if say: hoy.asc >> hoy.asc.txt

E

 

Hi Eric,

Thank you for the idea.
I uploaded the file.
Please see the same.

Regards
HARI

 

hi h,
Created the model, looks a little basic but it works.
E

 

Hi Eric,

Thank you very much.
May I know how to avoid the undershoot and get a neat signal.

Regards
HARI

 

hi,
If you disconnect S2_in, the Vin input is appearing on S2 pin.
I suspect the 719 model.??
E

 

hi hoy,
Try this added R3

E

 

Hi Eric,

Thank you it is working.
May I know how that resistor is solving the issue?

Regards
HARI

 

hi h,
Checking with the LTS current paths, you can see that switching the load cap and also the internal loading of the 719 model was feeding back into the L:T1803 output causing it to create the 'blip'.
For a test reduce the R3 to say 1R and use LTS to show the current thru R3.

E
With R3 = 1ohm current.

 

Hi Eric,
Thank you.
Regards
Hari