Ok, that's a true beginner's question in VLSI.
If I use a certain technology to size my mosfets (eg TSMC 180nm), does the size indicate the minimum size and also the minimum increment of the IC structures?
I mean, in my design can I make the 180nm gate and some other structure (e.g. metallization or other) 190nm? Or, can I realite the gate with 190nm? Could I produce ICs with this size? Or do I always have to use multiples of 180nm?

Thanks.

 

The number used to identify a process node used to represent the minimum feature size which was typically the gate length. At 180nm, the manufacturers were still using "honest" numbers. With the latest process generations, it's all marketing and they can use any number they want.

This is thanks to TSMC who started fudging numbers at around 22nm when they implemented tighter pitches on the frontend for their finFETs, but left the higher layers at the previous node dimensions. They got improved transistor performance, but no area improvement. Intel never played those games (until 10nm). It targeted about a 50% area reduction between process generations.

To answer your question. All layers except polysilicon, or whatever working metal they use for gates, feature sizes will be larger than the nominal process node number and they won't be multiples of the node dimension. In fact, the minimum dimensions of some feature sizes will be significantly larger than the process node number.

If you're talking about making your own ICs, not likely. You'd need an x-ray light source, plates, furnace, a process recipe, etc.

 

Still waiting for the desktop Mr IC unit, where I give it some rocks and my CAD files and it spits out a chip.

 

Intel never played those games (until 10nm). It targeted about a 50% area reduction between process generations.

Technically, TSMC, Intel, IBM, Samsung, etc. have all "played those games" since the early 2000s. Currently, all of the FinFET technologies hover around the geometric size of 40-60 nm, but have the performance equivalent of the node size, if you were using "traditional" FET technologies. So a "7nm FinFET" chip is about 50x50 in physical area, but acts like it has a 7nm gate size. The claim that they're "just marketing" is not true. Deceptive, yes, but the node sizes actually do still mean something.

Still waiting for the desktop Mr IC unit, where I give it some rocks and my CAD files and it spits out a chip.

And power it with your desktop "Mr Fusion," I presume? Or do you not want to risk sending your chips back in time?


Edit: changed a statement from "late 90s" to "early 2000s" for accuracy correction

 

And power it with your desktop "Mr Fusion," I presume? Or do you not want to risk sending your chips back in time?

Not a problem as long as I keep it away from my flux capacitor.

 

Technically, TSMC, Intel, IBM, Samsung, etc. have all "played those games" since the early 2000s [snip] Deceptive, yes, but the node sizes actually do still mean something.

I worked in that industry from the early 80's until 10nm. Intel's representation of process node feature size was accurate until they renamed their 10nm process to Intel7 to start using the same bogus process node naming that TSMC has been using since around 22nm.

In some earlier nodes, the effective gate length was actually smaller than what was drawn.

 

It's sort of strange that bragging rights for node size still seems to be important while most chip shortages are in the much older mature nodes with expected oversupply in advanced nodes on the horizon.
https://www.finder.com.au/micron-warning-has-chip-stocks-falling-again

Shares of Micron Technology (MU) and other semiconductor stocks are losing ground today after the semiconductor maker warned that demand is falling and sales will be lower in the current quarter.

https://www.barrons.com/articles/micron-earnings-chip-tech-stocks-51656700163

Micron’s stark warning has triggered widespread selling of other chip and equipment stocks, with the SOX , the widely tracked semiconductor index, down 4.6%. Among other large-cap chip shares, Intel INTC –2.86% (INTC), Advanced Micro Devices AMD –3.66% ( AMD ), Qualcomm ( QCOM ), and Nvidia NVDA –4.20% (NVDA) are down about 4%. The contract chip manufacturer Taiwan Semiconductor (TSM) is down 6%, while Western Digital (WDC), which competes with Micron in flash memory, is off 6.5%

Equipment stocks are falling even harder on Micron’s comments on reduced capital equipment spending plans, with Applied Materials (AMAT) and ASML (ASML) off 6%, KLA (KLAC) down 7% and Lam Research nearly 8% lower.

 

The number used to identify a process node used to represent the minimum feature size which was typically the gate length. At 180nm, the manufacturers were still using "honest" numbers. With the latest process generations, it's all marketing and they can use any number they want.

It's Ok, but that number is always a reference, right? I can't go to less of 180nm, right?

To answer your question. All layers except polysilicon, or whatever working metal they use for gates, feature sizes will be larger than the nominal process node number and they won't be multiples of the node dimension. In fact, the minimum dimensions of some feature sizes will be significantly larger than the process node number.

Ok, I can to use any dimensions >= 180nm even if it is not a multiple of the minimum size.

If you're talking about making your own ICs, not likely. You'd need an x-ray light source, plates, furnace, a process recipe, etc.

I am beginner in VLSI and I only make some experiments.
Now I use the TMSC 180nm PMOS and NMOS in LT Spice and I manually set the L (always 180nm) and W of my mosfets.
For make some particural funcionality, I am tried to change the W dimensions and I am obtaing some analog features. I am getting the features i want this way.

Now, I would like to draw the geometry in Magic VLSI.
If one day I decided to have MOSIS made my chip, would this geometry be achievable? would it work as well as i simulate it?

 

Ok, I can to use any dimensions >= 180nm even if it is not a multiple of the minimum size.

No. There are other considerations.

Now I use the TMSC 180nm PMOS and NMOS in LT Spice and I manually set the L (always 180nm) and W of my mosfets.
For make some particural funcionality, I am tried to change the W dimensions and I am obtaing some analog features. I am getting the features i want this way.

If you use TSMC's process, you have to use their design rules.

If one day I decided to have MOSIS made my chip, would this geometry be achievable? would it work as well as i simulate it?

If you're not a foundry customer, you won't be given process parameters that would allow you to get realistic simulations.

If you have a contract with a foundry, they'll give you design rules and data to run simulations.

 

No. There are other considerations.
If you use TSMC's process, you have to use their design rules.

The rules is the Lambda rules? In this case...I should always use a multiple of 180!

If you're not a foundry customer, you won't be given process parameters that would allow you to get realistic simulations.

If you have a contract with a foundry, they'll give you design rules and data to run simulations.

This is reasonable, but shouldn't the parameters of technologies that are public (BSIM, PTM, Univerities) be as close as possible to those of the foundry? If I don't get realistic simulations, then how do MOSIS customers do? To my knowledge they do not have the parameters of technology in advance.

 

The rules is the Lambda rules? In this case...I should always use a multiple of 180!

No. They only use Lambda in school text books. In the real world, they use actual dimensions. Using multiples of the minimum design feature isn't something that manufacturers care about. What determines metal pitches, etc are things like resistance, capacitance, electromigration, manufacturing equipment, etc.

shouldn't the parameters of technologies that are public (BSIM, PTM, Univerities) be as close as possible to those of the foundry?

Maybe for old process technology like 180nm.

If I don't get realistic simulations, then how do MOSIS customers do? To my knowledge they do not have the parameters of technology in advance.

If they do performance or reliability verification, they have to have access to relevant process parameters. If they don't expose the actual parameters, they may have a way to encrypt/obscure relevant information.