VLSI Cadence simulation HW

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Brettjohnson7191

Joined Apr 28, 2022
23
Hello everyone I am in VLSI and we are given the task of using Cadence software to create a three input NAND gate and run simulations while changing the Width of the NMOS/PMOS and keeping the length constant. Our goal is to find the values for the Width that creates a delay of .3ns. now I finished the hw already but solved the problem by guess and check and it took a while. As powerful of a software as this is I would have to believe there is a way to sweep the variables to find the correct delay. If anyone knows how to do this and could explain how it would be a appreciated so I know how to do it in the future. Thanks!
 
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