Hey,

So i've been sorta thrown into the deep end in trying to figure out HDL programming. I know the basics and can write some simple programs.

However, i've got a question about programming an FPGA.

So i've got a spartan 3e and i am trying to figure out how to code some control for the LCD.

There's a bit of an initialization that needs to be run and i am not sure how to implement a one-time initialization in VHDL. My question is: where should i put this and whats the best way to implement it? Since everything runs at once (more or less), how do i make something happen once at the very beginning and not bothered again!?

Sorry, i'm not really this much of a programming noob... i just don't really have any sense about the code structure of VHDL.

Thanks in advance!

 

you can do something like an enable bit which you have at some initial state (like 0) when the code starts

you can code a module to run only when this signal is in that state - at the end of the module set the bit to a 1 and it should not run again.

whats good about doing it this way, is that you can monitor a reset line if you want, and have that but of code flip that bit low again if you need to, and re-initialize the LCD.

hopefully i was clear, and that was helpful to you

 

Hey thanks for the tips! It was definitely clear and helpful.

I initially started off thinking of doing something like that.

The problem i was having in my mind is that i would need a process block to do this, right? And then i'd assume that the only variable in the sensitivity list would be the clock. So i have to check the state of this enable bit EVERY clock cycle?!?

I am sure there is probably an elegant way to do it and that i am making a false assumption somewhere.... but thats why i am asking rather than writing stupid code haha!

Thanks again for the help.

 

i have only coded FPGAs in verilog - so your use of "process block" confuses me a bit - this may be a "module" in verilog.

and yes, you would need a specific circuit to do this, and it will take up gates and such in the FPGA.

YOU dont need to check the bit every edge, it will be automatically checked every edge and active ONLY when the bit is in its initial state.

worry first, about getting it to work, then worry about optimizing and eloquence...thats how i go about things at least.

 

also the list and block would be comprised of all the signals and inputs/outputs of the initialization

think of this bit i was talking about as an enable line.

so write the code to do the initialization, and then lump the whole thing inside some enable logic - so that it only runs when the bit is in a given state.

when the bit is not enabling the circuit - it will be running in quiescent mode essentially - and drawing next to no power from the device.

 

Sounds like a state machine (FSM) would be nice in the LCD case. Don't forget that it is not only going to be initialized, but also show some data depending on some input after the initialization. There are plenty of material on the net about FSM and VHDL.

Checking the clock every cycle is just what the flip-flops do all the time, that's in the nature of synchronous logic. To control that things happen when they are supposed to happen, you use control/enable signals to make things happen.

I hope your FPGA evaluation board came with manuals or training material, but if it is one of the more common boards, chances are good that you will find more on the net.