Facebook
Google
GitHub
Linkedin
Hello everyone, while studying vhdl i compiled some lines which seemed irrational to me
lets assume these types and signals
TYPE oned IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
TYPE twod IS ARRAY (3 DOWNTO 0, 7 DOWNTO 0) OF STD_LOGIC;
SIGNAL x : oned;
SIGNAL y : twod;
SIGNAL z : STD_LOGIC_VECTOR (7 DOWNTO 0);
and now we have these lines
z(6 DOWNTO 4) <= x(5 DOWNTO 3);
which gave this error (Target type ieee.std_logic_1164.STD_LOGIC_VECTOR in signal assignment is different from expression type)
so i assumed that the type oned is not std_logic_vector . but then i tried this line
z(6 DOWNTO 4) <= y(5 DOWNTO 3);
and it had no problem compiling even if i changed it in a crazy way like this
z(6 DOWNTO 4) <= y(55862 DOWNTO 3);
Can someone explain me what is going on ? i am really confused
lets assume these types and signals
TYPE oned IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
TYPE twod IS ARRAY (3 DOWNTO 0, 7 DOWNTO 0) OF STD_LOGIC;
SIGNAL x : oned;
SIGNAL y : twod;
SIGNAL z : STD_LOGIC_VECTOR (7 DOWNTO 0);
and now we have these lines
z(6 DOWNTO 4) <= x(5 DOWNTO 3);
which gave this error (Target type ieee.std_logic_1164.STD_LOGIC_VECTOR in signal assignment is different from expression type)
so i assumed that the type oned is not std_logic_vector . but then i tried this line
z(6 DOWNTO 4) <= y(5 DOWNTO 3);
and it had no problem compiling even if i changed it in a crazy way like this
z(6 DOWNTO 4) <= y(55862 DOWNTO 3);
Can someone explain me what is going on ? i am really confused
