VHDL Code, when I try to simulate it, the signals does not work, losses, show a orange color

[Simulation error](https://i.stack.imgur.com/5bPNK.png)

Im using a Nexys 3 Spartan 6 Lower Power XC6SLX16L

the idea of the program is with a timer counter with specific conditions with the bottoms

Here is my code:


```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity structural is
Port (
up : in STD_LOGIC;
down : in STD_LOGIC;
right : in STD_LOGIC;
left : in STD_LOGIC;
reset : in STD_LOGIC;
clock : in STD_LOGIC;
anodes : out STD_LOGIC_VECTOR (3 downto 0);
cathodes : out STD_LOGIC_VECTOR (7 downto 0)
);
end structural;

architecture behavioral of structural is
signal clock_dis, clock_pul: std_logic;
signal pun1, pun2, pun3, code: std_logic_vector(3 downto 0);

begin
slowClockProcess: process(clock)
variable countFastCycles: integer range 0 to 50000 := 0; -- Divide the frequency by half
variable countFastCycles3: integer range 0 to 5000000 := 0; -- Divide the frequency by half
begin
if rising_edge(clock) then
countFastCycles := countFastCycles + 1;
countFastCycles3 := countFastCycles3 + 1;

if countFastCycles = 50000 then
clock_dis <= NOT clock_dis; -- Generate rising/falling edge for displays
countFastCycles := 0;
end if;

if countFastCycles3 = 5000000 then
clock_pul <= NOT clock_pul; -- Generate rising/falling edge for buttons
countFastCycles3 := 0;
end if;
end if;
end process slowClockProcess;

count: process(up, down, right, left, reset, clock)
variable counter: integer := 0;
begin
if rising_edge(clock) then
if reset = '1' then
counter := 0; -- Reset the counter
else
if up = '1' then
counter := counter + 1;
end if;

-- Decrement the counter
if down = '1' then
counter := counter - 1;
end if;

-- Increment the counter by 10 units
if right = '1' then
counter := counter + 10;
end if;

-- Decrement the counter by 10 units
if left = '1' then
counter := counter - 10;
end if;

-- Ensure the counter is within the range [0, 999]
if counter < 0 then
counter := 0;
elsif counter > 999 then
counter := 999;
end if;

pun1 <= std_logic_vector(to_unsigned(counter / 100, 4));
pun2 <= std_logic_vector(to_unsigned((counter / 10) mod 10, 4));
pun3 <= std_logic_vector(to_unsigned(counter mod 10, 4));
end if;
end if;
end process count;

seqDisplayProcess: process(clock)
variable numDisplay: integer range 0 to 4 := 0;
begin
if rising_edge(clock_dis) then
if numDisplay = 0 then
anodes <= "1011";
code <= pun1;
elsif numDisplay = 1 then
anodes <= "1101";
code <= pun2;
elsif numDisplay = 2 then
anodes <= "1110";
code <= pun3;
else
anodes <= "1111";
code <= "0000";
end if;

numDisplay := numDisplay + 1;

if numDisplay > 3 then
numDisplay := 0;
end if;
end if;
end process seqDisplayProcess;

-- BCD to 7-segment decoder
cathodes <= "00000011" when code = "0000" else -- Display number 0
"10011111" when code = "0001" else -- Display number 1
"00100101" when code = "0010" else -- Display number 2
"00001101" when code = "0011" else -- Display number 3
"10011001" when code = "0100" else -- Display number 4
"01001001" when code = "0101" else -- Display number 5
"01000001" when code = "0110" else -- Display number 6
"00011111" when code = "0111" else -- Display number 7
"00000001" when code = "1000" else -- Display number 8
"00001001" when code = "1001" else -- Display number 9
"00000000"; -- Default case
end behavioral;

```

The signals are losess i dont know why

I didnt found a sintaxis error, i tried changing everything i hope someone can help me, thanks a lot

Greetings from Colombia.