Very Simple Automatic Gain Controller (AGC) Circuit Design

Discussion in 'General Electronics Chat' started by botey, Mar 25, 2017.

  1. botey

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  2. crutschow

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    That is likely the result of the non-linearity of the FET resistance with signal voltage and polarity.

    Try to keep the AC voltage at the FET drain to be no more than 10 mV peak or so to minimize such distortion.
    Your design has about 200mV peak across the FET, if my calculations are correct.
    So a change in the circuit would be required so that the FET voltage is lower (and preferably doesn't change significantly with input voltage).

    Here's an example design that keeps the FET voltage constant.

    upload_2017-3-25_13-54-27.png
     
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  3. ian field

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    There used to be some neat ICs that pretty much did it all for you - but most of them are discontinued now. The long gone CA3080 was one of the best known, the LM13700 might still be obtainable.

    There are various audio amplifier chips with DC volume control - The BTL types are best avoided, single ended amplifiers are simpler to design around.
     
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  4. botey

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  5. botey

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  6. ian field

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    The overlapping circles have the gain control line leading straight to them.

    AFAICR: it basically just varies the bias current to the output pair.

    There is a type that controls gain by varying bias in the input stage - but I can't remember the type number.
     
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  7. AlbertHall

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  8. botey

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  9. botey

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  10. crutschow

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    The maximum gain is determined by the gain-bandwidth (GBW) of the op amp.
    The bandwidth equals the GBW divided by the close-loop gain, so the op amp circuit gain is limited usually by the bandwidth you need.

    Your modified circuit does help the problem but the voltage across the FET still varies with the input signal, which is not desirable.
     
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  11. AlbertHall

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    You can remove any DC offset by capacitor coupling the output.
     
  12. botey

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  13. botey

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  14. crutschow

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    I don't think the simulation has run long enough for the large time-constant of C2 and the scope input resistance to settle to its final DC state.
    Try connecting a 10kΩ resistor from the output of C2 to ground and see if that changes things.
     
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  15. botey

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  16. botey

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  17. KeepItSimpleStupid

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  18. AlbertHall

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    You have a capacitor directly connected to the gate of the FET. This to some extent negates the effect of the resistor between drain and gate. You need a resistor between the capacitor and the gate.
     
  19. ian field

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    A Gilbert cell is another gain control block - its not easy to do without a balanced output transformer, so no DC offset.

    Pretty big transformer unless you amplitude modulate an RF carrier and detect the modulation after the gain control block...........
     
  20. botey

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