Very Simple Automatic Gain Controller (AGC) Circuit Design

crutschow

Joined Mar 14, 2008
24,403
That is likely the result of the non-linearity of the FET resistance with signal voltage and polarity.

Try to keep the AC voltage at the FET drain to be no more than 10 mV peak or so to minimize such distortion.
Your design has about 200mV peak across the FET, if my calculations are correct.
So a change in the circuit would be required so that the FET voltage is lower (and preferably doesn't change significantly with input voltage).

Here's an example design that keeps the FET voltage constant.

upload_2017-3-25_13-54-27.png
 

ian field

Joined Oct 27, 2012
6,539
Hello!

This is my attempt at designing a very simple AGC circuit. I configured the JFET like that to change its resistance value automatically and affect the gain of the amplifier U2A. I used U2B to give no amplification for peak input voltages of 0.356V or above. D1 is used to provide negative voltage for the and R7 and C1 to change it to DC. I'm thinking of changing C1 to a larger value to increase the attack time to prevent a rapid change in the gain.
I'm concerned about the output signal of this circuit. For example; As you can see in the file named input 1, with a peak input voltage of 0.356V, the positive peak is less than the negative peak. I do not know why this is happening. I really would love to know the reason behind that.
I have attached pdf files named input 1, input 2 and input 3 which show the testing peak input voltages of 0.356, 0.2 and 0.1 respectively.
Channel 1 shows the input signal, Channel 2: output, Channel 3: DC from R7 and C1 network.
I would love to know if there is a flaw in this circuit or if there is something I forgot to consider about. Are there any necessary improvements I should do?

Thank you!
There used to be some neat ICs that pretty much did it all for you - but most of them are discontinued now. The long gone CA3080 was one of the best known, the LM13700 might still be obtainable.

There are various audio amplifier chips with DC volume control - The BTL types are best avoided, single ended amplifiers are simpler to design around.
 

ian field

Joined Oct 27, 2012
6,539
Thank you Ian Field! I can find the LM13700 IC on ebay here: http://www.ebay.co.uk/sch/i.html?_from=R40&_trksid=p2050601.m570.l1313.TR1.TRC0.A0.H0.XLM13700.TRS0&_nkw=LM13700&_sacat=0
But I would like to understand the reference typical application design from the datasheet. Link: http://www.ti.com/lit/ds/symlink/lm13700.pdf. I have marked some parts of the circuit that I would like to understand properly. What would be the meaning of the symbol marked in yellow? The components marked in pink and green, what exactly is their job?
The overlapping circles have the gain control line leading straight to them.

AFAICR: it basically just varies the bias current to the output pair.

There is a type that controls gain by varying bias in the input stage - but I can't remember the type number.
 

crutschow

Joined Mar 14, 2008
24,403
..........
I used another Op-amp (U1C) to compensate for the attenuation caused by the voltage divider. I configured U1B to give a huge amount of gain of 144. Do you think it can do it? Couldn't find maximum gain limitation on the datasheet. TL074: http://www.ti.com/lit/ds/symlink/tl074a.pdf
I have attached the modified circuit here.
The maximum gain is determined by the gain-bandwidth (GBW) of the op amp.
The bandwidth equals the GBW divided by the close-loop gain, so the op amp circuit gain is limited usually by the bandwidth you need.

Your modified circuit does help the problem but the voltage across the FET still varies with the input signal, which is not desirable.
 

crutschow

Joined Mar 14, 2008
24,403
I already have C2 as an AC coupling capacitor when adding the resistor. Not sure if it is a software issue or not. You may look at the attached picture below
I don't think the simulation has run long enough for the large time-constant of C2 and the scope input resistance to settle to its final DC state.
Try connecting a 10kΩ resistor from the output of C2 to ground and see if that changes things.
 

AlbertHall

Joined Jun 4, 2014
9,331
As you already know, the modified circuit shown in the picture named Modified 1 has very little distortion due to the small input signal caused by the voltage divider. To totally eliminate the distortion, I added a resistor between the drain and the gate as suggested by AlbertHull. To prevent the DC offset, I added the low pass filter. Now both the distortion and DC offset are completely gone as you can see in the attached picture named part 2-2 below. It takes a little bit of time for the DC offset to completely disappear though.
Update: At higher frequencies (above 5KHz) the detector network (R7, C1 and D1) reacts slower. Not exactly sure why. Also the distortion starts to appear but not by much. Just by a tiny bit.
You have a capacitor directly connected to the gate of the FET. This to some extent negates the effect of the resistor between drain and gate. You need a resistor between the capacitor and the gate.
 

ian field

Joined Oct 27, 2012
6,539
You can remove any DC offset by capacitor coupling the output.
A Gilbert cell is another gain control block - its not easy to do without a balanced output transformer, so no DC offset.

Pretty big transformer unless you amplitude modulate an RF carrier and detect the modulation after the gain control block...........
 
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