I'm programing in Verilog HDL and am having some problems with my carry out. I'm new to verilog and an trying to learn.
I am suppose to write a verilog module for the full adder subcircuit and write a top-level verlilog module that instances four instances of a full adder.
Soo basically I can get it to add and carry but once it need to carry to the fifth light I run into problems.
This is what I have so far
module add(Ci,A,B,S,Co);
input Ci;
input [3:0] A;
input [3:0] B;
output [3:0] S;
output Co;
assign S = Ci+(A+B);
assign Co = (~(S)&B)|((S)&Ci);
endmodule
module part3(SW,LEDR,LEDG);
input [8:0] SW;
output [8:0] LEDR;
output [4:0]LEDG;
assign LEDR=SW;
add (SW[8],SW[7:4],SW[3:0],LEDG[3:0],LEDG[4]);
endmodule
Any help would be appreciated!!
I am suppose to write a verilog module for the full adder subcircuit and write a top-level verlilog module that instances four instances of a full adder.
Soo basically I can get it to add and carry but once it need to carry to the fifth light I run into problems.
This is what I have so far
module add(Ci,A,B,S,Co);
input Ci;
input [3:0] A;
input [3:0] B;
output [3:0] S;
output Co;
assign S = Ci+(A+B);
assign Co = (~(S)&B)|((S)&Ci);
endmodule
module part3(SW,LEDR,LEDG);
input [8:0] SW;
output [8:0] LEDR;
output [4:0]LEDG;
assign LEDR=SW;
add (SW[8],SW[7:4],SW[3:0],LEDG[3:0],LEDG[4]);
endmodule
Any help would be appreciated!!
