For class, we are learning a little bit of Verilog and using ModelSim to code it in. I needed some assistance/guidance on how to code buses. I just can't seem to understand it fully. Basically, I have a 1-bit adder already coded:

module Bit1Adder (x1, x2, cin, cout, sum);
input x1, x2, cin;
output cout, sum;
assign cout = ((x1 & x2) | (cin & (x1 ^ x2)));
assign sum = (x1 ^ x2) ^ cin;
endmodule

Now, using this I want to create a 16-bit cascading adder. So for that, I have this so far:

`include 1BitAdder.v
module Adder16Bit 

Bit1Adder Adder0  (a, b, cin, sum0, cout0);
Bit1Adder Adder1  (a, b, cout0, sum1, cout1);
Bit1Adder Adder2  (a, b, cout1, sum2, cout2);
Bit1Adder Adder3  (a, b, cout2, sum3, cout3);
Bit1Adder Adder4  (a, b, cout3, sum4, cout4);
Bit1Adder Adder5  (a, b, cout4, sum5, cout5);
Bit1Adder Adder6  (a, b, cout5, sum6, cout6);
Bit1Adder Adder7  (a, b, cout6, sum7, cout7);
Bit1Adder Adder8  (a, b, cout7, sum8, cout8);
Bit1Adder Adder9  (a, b, cout8, sum9, cout9);
Bit1Adder Adder10 (a, b, cout9, sum10, cout10);
Bit1Adder Adder11 (a, b, cout10, sum11, cout11);
Bit1Adder Adder12 (a, b, cout11, sum12, cout12);
Bit1Adder Adder13 (a, b, cout12, sum13, cout13);
Bit1Adder Adder14 (a, b, cout13, sum14, cout14);
Bit1Adder Adder15 (a, b, cout14, sum15, cout15);

***I have it set up so all the inputs on the adders are the same (a, b) and then the Carry-Out (cout) of each Adder feeds into the Carry-In of the next Adder.

My question is that how do I use/set up buses to finish the rest of this correctly?

**Would it be something like this:

module Bit16Adder (a, b, cin, cout, sum);
input [15:0] a;
input [15:0] b;
input cin;
output [15:0] sum;
output cout;

This seems to me to be somewhat correct, but I feel I have something missing or something just not right about this.

Please guide me in the right direction and my apologizes for the long post.

 

Hi,
So you have 1 bit adder.
You have the 16 bit module ready with its in and out ports (yes, it's correct what you wrote).
All you need to do is connect the wires b/w the adders inside...
(i.e. connect x1 from the input to Adder0 port a)
btw, instead of making sure that your ports has the same order, use dot '.' for the internal port which you connect outside.
Bit1Adder Adder0 (.x1(a), .x2(b), .cin(cin), .cout(sum0), .sum(cout0));

 

Hi,
So you have 1 bit adder.
You have the 16 bit module ready with its in and out ports (yes, it's correct what you wrote).
All you need to do is connect the wires b/w the adders inside...
(i.e. connect x1 from the input to Adder0 port a)
btw, instead of making sure that your ports has the same order, use dot '.' for the internal port which you connect outside.
Bit1Adder Adder0 (.x1(a), .x2(b), .cin(cin), .cout(sum0), .sum(cout0));

Thanks for your post and help.

Could you provide a quick code example with your answer, I grasp things better when I see an example of it, that way I can implement it better in my own code.

 

There's a 4bit using 1bit adder: (no copyrights for me,a simple google search)
module addbit (
a , // first input
b , // Second input
ci , // Carry input
sum , // sum output
co // carry output
);
//Input declaration
input a;
input b;
input ci;
//Ouput declaration
output sum;
output co;
//Port Data types
wire a;
wire b;
wire ci;
wire sum;
wire co;
//Code starts here
assign {co,sum} = a + b + ci;

endmodule // End of Module addbit

Now if you want to use this 1 bit there's the big module:
module adder_explicit (
result , // Output of the adder
carry , // Carry output of adder
r1 , // first input
r2 , // second input
ci // carry input
);

// Input Port Declarations
input [3:0] r1 ;
input [3:0] r2 ;
input ci ;

// Output Port Declarations
output [3:0] result ;
output carry ;

// Port Wires
wire [3:0] r1 ;
wire [3:0] r2 ;
wire ci ;
wire [3:0] result ;
wire carry ;

// Internal variables
wire c1 ;
wire c2 ;
wire c3 ;

// Code Starts Here
addbit u0 (
.a (r1[0]) ,
.b (r2[0]) ,
.ci (ci) ,
.sum (result[0]) ,
.co (c1)
);

addbit u1 (
.a (r1[1]) ,
.b (r2[1]) ,
.ci (c1) ,
.sum (result[1]) ,
.co (c2)
);

addbit u2 (
.a (r1[2]) ,
.b (r2[2]) ,
.ci (c2) ,
.sum (result[2]) ,
.co (c3)
);

addbit u3 (
.a (r1[3]) ,
.b (r2[3]) ,
.ci (c3) ,
.sum (result[3]) ,
.co (carry)
);

endmodule // End Of Module adder