# Verilog code help

#### dumindu89

Joined Oct 28, 2010
113
Help me to write the verilog code for a decade down counter with asynchronous parallel load and borrow. The operation is similar to the 74192 IC.

I can write the code for decade down counter.
But I have no idea how to implement the parallel load inputs and the borrow output.

Please help me to write the complete verilog code for this. Any suggestion? ( I am using Altera MAX II - EPM240T200C5N CPLD)

#### WBahn

Joined Mar 31, 2012
25,566
Post the code that you can write and then clearly describe the behavior need for the remaining functions. We can proceed from there.

#### dumindu89

Joined Oct 28, 2010
113
Hello!
I decided to write the code using VHDL.

I found a VHDL code for a frequency divider (divided by 25) and I modified it to divide the frequency by 80. (I need a divided by 80 fixed divider too).

Rich (BB code):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity divby_80 is
Port (
clk             : in  std_logic;
reset: in std_logic;
clk_out       : out std_logic

);
end divby_80;

architecture divby_80_a of divby_80 is
process(reset,clk)
begin
if (reset='0') then
count<=0;
clk_out<='0';
elsif rising_edge(clk) then
if (count=79) then
clk_out<=NOT(clk_out);
count<=0;
else
count<=count+1;
end if;
end if;
end process;
end divby_80_a;
I have two points in this code to understand.
why do we use "clk_out<=NOT(clk_out);" and why do we use a reset?
Once I finished the code for this fixed divider I can move to the programmable divider which is more complex.

I found this code too for a fixed frequency divider

Rich (BB code):
 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity clk_gen is
port(   Clk : in std_logic;
Clk_mod : out std_logic;
divide_value : in integer
);
end clk_gen;

architecture Behavioral of clk_gen is

signal counter,divide : integer := 80;

begin

divide <= divide_value;

process(Clk)
begin
if( rising_edge(Clk) ) then
if(counter < divide/2-1) then
counter <= counter + 1;
Clk_mod <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
Clk_mod <= '1';
else
Clk_mod <= '0';
counter <= 0;
end if;
end if;
end process;

end Behavioral;

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#### guitarguy12387

Joined Apr 10, 2008
359
For educational purposes, yeah it will probably work fine.

You're basically using an register (with a clock enable) to 'flip' the the output signal ( clk_out<=NOT(clk_out) when a certain count value is reached. The reset is used to provide a known initial state.

There's a few practical things that make this not ideal for many applications on an FPGA (i.e. asynchronous resets are generally bad practice on FPGAs, you should use specialized clock resources for deriving clocks instead of fabric, etc.), but for slow speeds and many scenarios, it will probably work okay.

#### WBahn

Joined Mar 31, 2012
25,566
I don't think using asynchronous logic or gated clocks are safe at any speed in most FPGA designs. Being LUT based, logic signals in an FPGA are intrinsically glitchy.