Verilog hdl code help!

Discussion in 'Embedded Systems and Microcontrollers' started by badalandabad, Jan 25, 2011.

  1. badalandabad

    Thread Starter New Member

    Jul 1, 2008
    Can someone help me with these problems?

    1. A 4 bit up/down counter. Use asynchronous reset to initialize the counter. When a=1, counter increments. When a is 0, decrements.

    2. Implement an 8 input multiplexer. sel is the routing control signal while SOURCE0_IH TO SOURCE7_IH are signals to be routed.