Verilog hdl code help!

Thread Starter


Joined Jul 1, 2008
Can someone help me with these problems?

1. A 4 bit up/down counter. Use asynchronous reset to initialize the counter. When a=1, counter increments. When a is 0, decrements.

2. Implement an 8 input multiplexer. sel is the routing control signal while SOURCE0_IH TO SOURCE7_IH are signals to be routed.