Variable PWM generator

Thread Starter

Razah

Joined Feb 20, 2020
4
I need help with setting up pwm generator with variable frequency and duty cycle from around 10 Hz to 150 kHz, with important parameter of time 20 ns or less for the shortest pulse width. What kind of IC can i use in completing such circuit (not 555).< My profesor suggested using CD4538 IC >
 

danadak

Joined Mar 10, 2018
4,057
How do you want to control the frequency and duty cycle ? With pots or over RS232 or ?

Accuracy you need of freq and duty cycle ?


Regards, Dana.
 

Thread Starter

Razah

Joined Feb 20, 2020
4
Setting frequency and duty cycle with potentiometers. Only requirements are frequency range few Hz to 150kHz and minimal pulse width shorter than 20ns.
 

ronsimpson

Joined Oct 7, 2019
912
Setting frequency ...…. with potentiometers. …...… frequency range few Hz to 150kHz
Having a range of 10hz to 150khz on one know is too much. Most signal generators have 10:1 on the know.
In the picture the knob goes from 10 to 100 and switches do the x1, x10, x100, x1k, x10k.
1582316641930.png
 

danadak

Joined Mar 10, 2018
4,057
Something like this, one chip, simple dev board $ 10. POTS you supply.

https://www.cypress.com/documentation/development-kitsboards/cy8ckit-059-psoc-5lp-prototyping-kit-onboard-programmer-and

IDE (PSOC Creator) and compiler free. https://www.cypress.com/products/psoc-creator-integrated-design-environment-ide

Estimate maybe 12 lines of code to write, basically just to take A/D (POT) values
and do the calculation for values to write to DDS (frequency desired) and
PWM (Duty Cycle required).

The one thing I did not check is min 20 ns on PWM as configed. Is that at both 1 Hz and 150 Khz ?

1582317498079.png

Note right hand window, chip resources used/left. Still a lot left for other tasks, like LCD,
Counters, Timers, DAC, OpAmps, Comparators, logic, LUT.....

Accuracy of freq and duty cycle < .1% I think. I would have to run the numbers.


Regards, Dana.
 

danadak

Joined Mar 10, 2018
4,057
Based on 20 ns resolution, that implies 5 Mhz clock to PWM, so using combo of DDS and PWM
limited because of DDS clock accuracy limitations at higher freqs.

Maybe a better way is use two DDS, both synced, set at same desired freq, but using phase
control register in secondary DDS to control duty cycle, xoring their outputs to generate the
PWM stream.

The actual res would be much better than 20 nS, but overall res still set by A/.D resolution in
reading the pots.

Again this is single chip solution.

1582890709180.png


I have not built this, would have to try this out, but I think its straightforward
.

Regards, Dana,
 
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