Unmodulated Carrier Recovery

Discussion in 'The Projects Forum' started by matt111111, Nov 26, 2014.

  1. matt111111

    Thread Starter New Member

    Nov 26, 2014
    I am working on a carrier recovery design and have been experiencing issues. I have attached a block diagram of the design for reference.

    The primary issue is that PLL#3 does not lock continuously. This PLL will intermittently lock and is displayed by the lock detect indicator pulsing on and off.

    The general operation is: an unmodulated carrier is transmitted by another device and received at the antenna and designated F1. This signal is then down mixed to approx. 450 KHz. The 450 KHz signal is used as the oscillator input on PLL#3. PLL#3 controls a VCTCXO which is used to provide the appropriate reference clock for PLL/VCO#2.
    In order to achieve the initial lock we are working on the premise that the VCTXO will be at a max or min frequency limit when PLL#3 is not locked due to the tuning output being railed high or low. The objective is to lock the VCTCXO to the device that transmits the unmodulated carriers TCXO.

    Can anyone confirm the general theory/operation of this design is correct?

  2. DickCappels


    Aug 21, 2008
    The general theory sounds sound. Could it be that you have oscillation of the frequencies among the PLL's? You might need to reduce loop gain of some of the PLL's (use only the gain you need to attain the static phase error you need) and/or increase the separation of the poles in their low pass filters so as to prevent oscillation.

    The purpose of PLL #1 and #2 is not clear from your description. I might be a good idea to eliminate one or both of them if possible as they might be sources of instability, not to mention noise.
  3. matt111111

    Thread Starter New Member

    Nov 26, 2014
    Hi DickCappels

    PLL #1 can be ignored as it is only used to create a frequency shifted version of the carrier locked signal and re transmit it off the board. This PLL is currently disconnected.

    The purpose of PLL#2 is to down mix the RF input to a frequency that is an acceptable oscillator input frequency for PLL#3. Ideally if PLL#3 could take the high RF input freq PLL #2 wouldn't exist.