Hi, how can I simulate a 100MHz FM carrier wave and audio with spice? The AM simulation below works at 1MHz but slows to a crawl at 10 and crashes at 100 unless I let the PC sit for a minute or two. If I try to zoom in after its done, it seems to simulate the circuit again and goes through the same process.

 

Hi king
Post your LTS asc file.
E

 

Hi king
Post your LTS asc file.
E

 

Think about what you are asking it to do. You want to simulate a waveform at 100 MHz over a period of time corresponding to an audio signal at, say, 1 kHz. Let's say it needs to generate ten data points per cycle of the carrier over ten periods of the audio signal modulating it. That's one billion samples per second over ten milliseconds, or ten million sample points. Each sample point requires quite a bit of computation in order to solve the network equations with sufficient accuracy, which generally involves a time step significantly smaller than the sample spacing.

This is going to take some time.

You probably will need to dump results to an output file and then post-process the data in the file.

When I was designing ICs, we often had simulations of circuits that only had a few dozen transistors in them but that would take a day to get a decent simulation of events that only lasted a few hundred microseconds.

 

Try this for FM

 

Think about what you are asking it to do. You want to simulate a waveform at 100 MHz over a period of time corresponding to an audio signal at, say, 1 kHz. Let's say it needs to generate ten data points per cycle of the carrier over ten periods of the audio signal modulating it. That's one billion samples per second over ten milliseconds, or ten million sample points. Each sample point requires quite a bit of computation in order to solve the network equations with sufficient accuracy, which generally involves a time step significantly smaller than the sample spacing.

This is going to take some time.

You probably will need to dump results to an output file and then post-process the data in the file.

When I was designing ICs, we often had simulations of circuits that only had a few dozen transistors in them but that would take a day to get a decent simulation of events that only lasted a few hundred microseconds.

What time step is appropriate as good rule of thumb? Eric's circuit still takes a good 5-10 seconds but after it's loaded I can at least zoom in without it reprocessing everything. He has it set to 2n but at 25n or more the signal becomes garbage just like on the scope.

 

What time step is appropriate as good rule of thumb? Eric's circuit still takes a good 5-10 seconds but after it's loaded I can at least zoom in without it reprocessing everything. He has it set to 2n but at 25n or more the signal becomes garbage just like on the scope.

less than the period of the fastest simulated device frequency.

 

What time step is appropriate as good rule of thumb? Eric's circuit still takes a good 5-10 seconds but after it's loaded I can at least zoom in without it reprocessing everything. He has it set to 2n but at 25n or more the signal becomes garbage just like on the scope.

At 100 MHz, the period is 10 ns. You have to be at least twice that to capture all of the content at that frequency, even with infinite signal-to-noise ratio, so 5 ns is the slowest you can even, in theory, consider. But since you don't have infinite SNR, you need to sample faster than that. If possible, I like to sample at no less than 10x the highest frequency, though 5x is often good enough.

 

Try this for FM

I'm not quite sure what you are doing here.

Your expression for V(mod) should produce extremely high frequency content and by sampling it at 5ns intervals you are going to be extremely aliased.

What that your intention -- to use undersampling and intentional aliasing?

Perhaps I'm not understanding the use of the behavioral device model, which is something I haven't used for over twenty years or so, so here is what I'm thinking it should produce:

v(a) = 0.005*sin(2πf1*t)

where f1 = 10 kHz

v(mod) = 10 mV sin(2πfo(1+v(a))

where fo = 100 MHz

v(mod) = 10 mV sin(2πfo(1+0.005*sin(2πf1*t))

v(mod) = 10 mV sin(2πfo + 0.01πfo*sin(2πf1*t))

The first 2πfo is simply a static phase shift, but since fo is an integer, wo is an integer multiple of 2pi, so it goes away.

v(mod) = 10 mV sin(0.01πfo*sin(2πf1*t))

This is of the general form of

v(t) = A·sin(Θ(t))

The instantaneous frequency of this waveform is therefore the derivative of Θ(t), which is

Θ(t) = 0.01πfo*sin(2πf1*t)

f(t) = dΘ(t)/dt = 0.01πfo * cos(2πf1*t) * d(2πf1*t)/dt

f(t) = (0.01πfo) * (2πf1) * cos(2πf1*t)

f(t) = (0.02π²fo*f1) * cos(2πf1*t)

f(t) = 2π(0.01πfo*f1) * cos(2πf1*t)

So the peak cyclical frequency would seem to be

f3 = 0.01πfo*f1 = 0.01π 100 MHz * 10000 = 31.4 GHz

 

To test out my suspicion, I did the following:

First, I ran the original simulation and focused on the span between 3.5 µs and 4.5 µs.



I put markers at the actual sample points.

This has the hallmarks of a significantly aliased signal. We know the waveform should be a pretty clean sinusoid whose frequency is increasing and decreasing smoothly -- at least that is what I am assuming was intended.

Next, I zoomed in (on this same waveform) on two portions I want to explore at a higher sampling rate.

First, that central low frequency hump at about 3.86 µs, and second, the region over near 4.35 µs when the signal appears to be very small amplitude.




Now, if I'm right, the actual frequency of this signal is going to be about 30 GHz, which means that there will be about 3000 cycles of the waveform over a span of 0.1 µs, So let's zoom in even further.

For the top plot, I'll center things up at about 3.85 µs. If I want to limit the number of cycles displayed to about 30, then I need to adjust the span of the x-axis to about 1 ns. So let's go 3850 ns to 3851 ns.



As expected, we see a very flat signal at 6 mV.

For the bottom plot, I'll center things up at about 4.35 µs by going from 4350 ns to 4351 ns.



And here we see a signal that is basically non-existent.

But is this actually the case -- or are the signals just getting aliased down to DC?

Now, I reran the simulation, but set the sampling period to 2 ps and displayed them with these same limits:



I also put a pair of cursers to get a frequency measurement and, sure enough, it comes in right at 30 GHz. Also notice that the signal amplitude is right about the full 10 mV.

Doing the same for the bottom plot also reveals a ~30 GHz signal at the full amplitude.



So I think my suspicions are pretty well confirmed -- the simulation is not producing what was probably intended, but instead a signal that is up in the 30 GHz range but that is getting severally aliased by only sampling it at 500 MSa/s.

 

Since the TS is asking primarily about the speed of simulation, another thing to keep in mind is that running a simulation that is doing nothing but very simple math is stacking the odds hugely in favor of the simulator. As soon as you throw circuit components that now represent a network that has to be solved at every time step, things are going to slow down enormously.

 

If you have a true FM signal, the amplitude of the signal will be constant and only the frequency will change. This is a bit of a fib, because the fact that the frequency is changing means that the peaks of any given cycle won't exactly reach the full envelope amplitude, but they'll be pretty close unless the modulation depth is extreme.

So I set up a simulation by running the math backwards to get a 10 kHz modulating signal that takes a 100 MHz carrier up and down 2 MHz from the null.

Here is what I get when the frequency is a max:



Here is what I get when the frequency is a min:



Since the frequency is only varying by 2% from the carrier, zooming out shows no discernable frequency deviation.

Here's the controlled source that is generating the signal:



Note that 2% is a pretty hefty frequency deviation. FM broadcast stations are more like 0.05%.

I anyone would like, I can walk through the math that produced this "circuit".

 

I'm not quite sure what you are doing here.

Your expression for V(mod) should produce extremely high frequency content and by sampling it at 5ns intervals you are going to be extremely aliased.

What that your intention -- to use undersampling and intentional aliasing?

Perhaps I'm not understanding the use of the behavioral device model, which is something I haven't used for over twenty years or so, so here is what I'm thinking it should produce:

v(a) = 0.005*sin(2πf1*t)

where f1 = 10 kHz

v(mod) = 10 mV sin(2πfo(1+v(a))

where fo = 100 MHz

v(mod) = 10 mV sin(2πfo(1+0.005*sin(2πf1*t))

v(mod) = 10 mV sin(2πfo + 0.01πfo*sin(2πf1*t))

The first 2πfo is simply a static phase shift, but since fo is an integer, wo is an integer multiple of 2pi, so it goes away.

v(mod) = 10 mV sin(0.01πfo*sin(2πf1*t))

This is of the general form of

v(t) = A·sin(Θ(t))

The instantaneous frequency of this waveform is therefore the derivative of Θ(t), which is

Θ(t) = 0.01πfo*sin(2πf1*t)

f(t) = dΘ(t)/dt = 0.01πfo * cos(2πf1*t) * d(2πf1*t)/dt

f(t) = (0.01πfo) * (2πf1) * cos(2πf1*t)

f(t) = (0.02π²fo*f1) * cos(2πf1*t)

f(t) = 2π(0.01πfo*f1) * cos(2πf1*t)

So the peak cyclical frequency would seem to be

f3 = 0.01πfo*f1 = 0.01π 100 MHz * 10000 = 31.4 GHz

Thanks, this explanation made sense of some of the artifacts I'm seeing. I went over your numbers a few times and I think I understand what is going on.

What do you use to graph Θ(t) = 0.01πfo*sin(2πf1*t)? I want to compare the calculated function to the spice output if possible. Desmos works but is wonky with the zoom when fo and f1 are large.

 

You should also disable waveform compression.
It doesn't effect the computed waveform but affects how they are saved and displayed in the waveform viewer.

Add the following directive to the schematic:
.option plotwinsize=0

 

I'm not quite sure what you are doing here.

Nor me. Oops. I've now edited the asc file in post #5 to correct the behavioral voltage properties and specified the maximum time step as 1nS.

 

Nor me. Oops. I've now edited the asc file in post #5 to correct the behavioral voltage properties and specified the maximum time step as 1nS.

I don't see a difference in the file (or an indication that the post has been edited) -- you sure you hit 'Save'?

I'd recommend leaving the original file alone so that people that come along in the future can download it and follow the discussion. Post the updated version in a new post. That will also let people following the thread receive a notification. Cheers!

 

Recommendation noted.

 

Recommendation noted.

When you get a chance, would love to see your updated approach. The approach I used was a rather brute force approach to implement the math (though it does show how a quadrature-based modulator is motivated).

 

would love to see your updated approach.

Attached is the latest asc file.
An alternative approach would be to use the Modulate component in the LTS Special Functions folder.

 

Here's an example of the use of the Modulate component.