Universal Shift Register

Thread Starter

jegues

Joined Sep 13, 2010
733
A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallel load capability. Draw a circuit for such a shift register.

Okay, after doing some wiki'ing and some reading about shift registers I have better idea of what we're talking about, but it's still not crystal clear.

For a "parallel load capability" n-bit data items will be transmitted all at once using n seperate wires, thus the transfer is performed in parallel. Is this what I'm looking to accomplish? Or are they just trying to tell me that the shift register has the ability to accept a parallel input?

Also, if it's suppose to have the ability to shift both Left-to-Right and Right-to-Left so we must be talking about a bi-directional shift register, correct?

How do I figure out what gates/flip-flops I'm going to need for something like this?

Thanks again!
 

nyasha

Joined Mar 23, 2009
90
You will need two input gates gating into an OR gate which itself goes to the D flip flop. The two and gates are for either shifting right or shifting left. And then include parallel load cabapility as you would do any shift register.
 

Georacer

Joined Nov 25, 2009
5,182
Remember the last assignment you posted, about he MUX shifter? It could load directly from the 4 inputs, or slide them. Now what if you drove the output of the MUXs on D-FFs to store it for the rest of the clock cycle?
That would take care of the storing part.

But you also need to shift the data left, right or keep it intact for as much time needed.

Hmmm, the MUX you used has 3 more inputs, now that one will be occupied by the input. I wonder...
 

Thread Starter

jegues

Joined Sep 13, 2010
733
Here's what we've been given as solutions. (See figure attached)

Maybe from this we can devise a procedure for these types of problems and then I will actually understand what's happening and why.

Let me know what you think.
 

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Georacer

Joined Nov 25, 2009
5,182
Isn't a register supposed to be able to hold its data, without the need to refresh it on every clock cycle? Much like a Flip Flop.
I don't see that possibility in this circuit.

What have they told you about this in the class?

Note: Please remove the circuit schematic from the picture, as it propably refers to another exercise. But, do you know by any means, what it is supposed to represent?
 

Thread Starter

jegues

Joined Sep 13, 2010
733
Isn't a register supposed to be able to hold its data, without the need to refresh it on every clock cycle? Much like a Flip Flop.
I don't see that possibility in this circuit.

What have they told you about this in the class?

Note: Please remove the circuit schematic from the picture, as it propably refers to another exercise. But, do you know by any means, what it is supposed to represent?
Whoops, forget about the circuit in the figure, the text in the figure is all they give us. As I said our professor just reads powerpoint slides in class, he doesn't "teach" us anything.

EDIT: The figure above has been edited accordingly
 

Georacer

Joined Nov 25, 2009
5,182
So, can you come up with an idea of using D-FFs with the shifter circuit you did in the previous exercise?
("H" and "K" MUXs are not necessary.)
 

Thread Starter

jegues

Joined Sep 13, 2010
733
So, can you come up with an idea of using D-FFs with the shifter circuit you did in the previous exercise?
("H" and "K" MUXs are not necessary.)
I could understand the using the shifter circuit to shift bits left and right, but I don't know what roles the D flip-flops are playing. I'm guessing they're are used as memory for something, but I'm not entirely sure what.
 

Georacer

Joined Nov 25, 2009
5,182
A register's primary function is to load X bits of information on demand (Load signal) and hold that information indefinitely. It must also output that information continuously. D-FF are ideal for that job.
 

Thread Starter

jegues

Joined Sep 13, 2010
733
A register's primary function is to load X bits of information on demand (Load signal) and hold that information indefinitely. It must also output that information continuously. D-FF are ideal for that job.
Here's the circuit I keep coming across over and over. It's suppose to be able to shift both left and right, but it has a serial input.

Don't we want parallel-load input?

I'm guessing we're just gonna have to tweak this one a little bit.
 

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Georacer

Joined Nov 25, 2009
5,182
Remember the last assignment you posted, about he MUX shifter? It could load directly from the 4 inputs, or slide them. Now what if you drove the output of the MUXs on D-FFs to store it for the rest of the clock cycle?
That would take care of the storing part.

But you also need to shift the data left, right or keep it intact for as much time needed.

Hmmm, the MUX you used has 3 more inputs, now that one will be occupied by the input. I wonder...
Imagine the following: You have 4 side-by-side D-FFs, which will store any information you give them on their input, every clock cycle.

They take input from the output of one 4-to-1 MUX, one for each FF. Therefore, the content of the FF will be the output of the MUX.
Now the point is what the MUX will give. Well, the question is what we want it to give for each control option. The output of the MUX is controlled by a 2-bit digit S.

If S=00, we can specify that our register won't change its content. Thus the MUX's must output the same data as the D-FF have. Thus the 00 input of the MUXs will be the output of the D-FFs.

Do the rest yourself:

If for S=01 we want the register to shift right, what will be the input of the 01 pin of the MUX?

If for S=10 we want the register to shift left, what will be the input of the 10 pin of the MUX?

If for S=11 we want the register to load the input data, what will be the input of the 11 pin of the MUX?

Is that clear?
 

Thread Starter

jegues

Joined Sep 13, 2010
733
Imagine the following: You have 4 side-by-side D-FFs, which will store any information you give them on their input, every clock cycle.

They take input from the output of one 4-to-1 MUX, one for each FF. Therefore, the content of the FF will be the output of the MUX.
Now the point is what the MUX will give. Well, the question is what we want it to give for each control option. The output of the MUX is controlled by a 2-bit digit S.

If S=00, we can specify that our register won't change its content. Thus the MUX's must output the same data as the D-FF have. Thus the 00 input of the MUXs will be the output of the D-FFs.

Do the rest yourself:

If for S=01 we want the register to shift right, what will be the input of the 01 pin of the MUX?

If for S=10 we want the register to shift left, what will be the input of the 10 pin of the MUX?

If for S=11 we want the register to load the input data, what will be the input of the 11 pin of the MUX?

Is that clear?
That's much more clear, I'll draw up a schematic and post my results! Stay tuned!
 

Georacer

Joined Nov 25, 2009
5,182
You sure made a mess there...

Let's recap: Your current number is inside the FFs. This is the information you keep or shift. W is the input that is used only on 11 when you Load. Y is read straight from the Q output of the FFs.

The input of the D-FF comes only from the output of the MUX. Honestly, on what basis did you leave D1 and D4 hanging and D2 and D3 controlled by the previous FF? Each FF is independant.

When shifting, the data you want a FF to take, comes from a previous or next FF, not the input.
I aslo think that you should feed 0 on the edges, not recycle the opposite bit.

You should propably google your projects a little more. They are quite common and there are ample examples out there.
 

Thread Starter

jegues

Joined Sep 13, 2010
733
You sure made a mess there...

Let's recap: Your current number is inside the FFs. This is the information you keep or shift. W is the input that is used only on 11 when you Load. Y is read straight from the Q output of the FFs.

The input of the D-FF comes only from the output of the MUX. Honestly, on what basis did you leave D1 and D4 hanging and D2 and D3 controlled by the previous FF? Each FF is independant.

When shifting, the data you want a FF to take, comes from a previous or next FF, not the input.
I aslo think that you should feed 0 on the edges, not recycle the opposite bit.

You should propably google your projects a little more. They are quite common and there are ample examples out there.
The only examples I can find are parallel loaded shift register that only shifts in one direction.

Or serial loaded shift register that can shift in both directions.

This is extremely frustrating. Our textbook doesn't give us any help on any of this stuff.
 

Georacer

Joined Nov 25, 2009
5,182
Take it easy. Think about it once more.

I will call "i" the arbitrary bit number of the information. If the data is \(A_4A_3A_2A_1\), Ai represent any of the afforementioned bits.

FFi stores the i-th bit of the nuber. It is your box to store it and it will have inside it exactly what input Di is fed.

If you want to keep the same bit in the box (S=00), all you have to do is feed Di with Qi. What comes in comes out. Simple, no?

If you want to shift left your data (S=01), you want the box i to have the bit that the box i-1 previously had. Therefore you feed Di with \(Q_{i-1}\).

If you want to shift right your data (S=10), you want the box i to have the bit that the box i+1 previously had. Therefore you feed Di with \(Q_{i+1}\).

If you want to load an input Wi directly in the FFi (S=11), you have to feed Di with the signal Wi.

You see that there are 4 options for what you will load in the FFi. The selection will be realized by one MUX for each FF.

Try once more. I think you will get it this time.
 

Thread Starter

jegues

Joined Sep 13, 2010
733
Take it easy. Think about it once more.

I will call "i" the arbitrary bit number of the information. If the data is \(A_4A_3A_2A_1\), Ai represent any of the afforementioned bits.

FFi stores the i-th bit of the nuber. It is your box to store it and it will have inside it exactly what input Di is fed.

If you want to keep the same bit in the box (S=00), all you have to do is feed Di with Qi. What comes in comes out. Simple, no?

If you want to shift left your data (S=01), you want the box i to have the bit that the box i-1 previously had. Therefore you feed Di with \(Q_{i-1}\).

If you want to shift right your data (S=10), you want the box i to have the bit that the box i+1 previously had. Therefore you feed Di with \(Q_{i+1}\).

If you want to load an input Wi directly in the FFi (S=11), you have to feed Di with the signal Wi.

You see that there are 4 options for what you will load in the FFi. The selection will be realized by one MUX for each FF.

Try once more. I think you will get it this time.
Okay here's my second attempt. I appologize again if it is a little messy but this is the way only way I could draw it.

Please take your time reading it. I really hope I got it on this one!
 

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Georacer

Joined Nov 25, 2009
5,182
That comes with experience and practice. Basic digital circuits like registers, counters and shifters are easy to remember after some practice. Or you can choose not to remember them at all, after you are examine on them of course. The reason is that either they come "as is" in one separate IC, or you can easilly look them up on the net. You don't have to overload your brain with information that you can easilly look up.

By the way, I still wonder how can Bill remember the 555 layout combinations. I have to triple check the connections every time I build a clock.
 
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