Ah cool, That's a really nice way to put it! Thank you

Before the 65nm node, designers were more concerned with dynamic power dissipation. At 65nm, leakage accounted for more than half of the power dissipation. That's when they started looking for ways to reduce leakage.

 

Before the 65nm node, designers were more concerned with dynamic power dissipation. At 65nm, leakage accounted for more than half of the power dissipation. That's when they started looking for ways to reduce leakage.

Exactly what I have been trying to get across. Reducing leakage by using a different design, in addition to reducing the power needed to change logic states. The reduced voltage must be used because of the changes.