Hello,

I have a gap in my knowledge that I'm having trouble bridging.

In a topology like this one:


Figure 2 from: https://e2e.ti.com/blogs_/b/powerhouse/posts/ldo-basics-dropout

This is what I currently believe:
1. When the positive input to the opamp is higher then Vref, the output of the opamp will be high.
2. When the output of the opamp is high, the mosfet will conduct
3. When the mosfet is conducting, the voltage at Vout will increase
4. When the voltage at Vout increases, the voltage at the positive terminal of the opamp will increase, resulting in an unstable system (since we are trying to drive the difference between opamp + and - terminals to zero).

Apparently I am wrong, according to the article, and according to the modeling I've done in Multisim.
What am I missing?

 

The opamp is open loop. there is no feedback. The output essentially has only has two values:

1. As close to the positive rail as possible. This may, depending on the opamp, be several volts below the positive rail
2. As close to the negative rail, ground, as possible. This may, depending on the opamp be several hundred millivolts above the negative rail.

If either input, Vref or the voltage at the junction of R1 and R2 is outside the common mode range there can be an inversion of the amplifiers normal behavior.

We need more information:

1. What are you trying to do?
2. What opamp are we talking about

 

Thanks for answering. I'm only trying to understand the behavior of a Enhancement mode PMOS Low Drop Out circuit within the common mode range.

According to my (likely faulty) understanding, the circuit does not perform as a LDO voltage regulator, as it does not regulate the output to any specific value.

I don't have specific opamps in mind, as that would add unnecessary additional complexity. (Wouldn't it?)


Edit:
If the positive input of the opamp is already too high (according to my original post's example), the mosfet resistance should increase, causing the current to lower. This would reduce the positive input of the opamp voltage and regulate the output as desired, but if my understanding is correct, the mosfet resistance is going low, causing high current instead.

 

>2. When the output of the opamp is high, the mosfet will conduct

It is a P channel, so it is the other way around

So basically, when the voltage gets larger than a certain value, the mosfet turns off.

You'd usually have a cap on the output to smooth the rise/fall time

We have a circuit at my work that has been used since the 90s which uses this technique to regulate the output voltage, and a very similar way to regulate max current.

 

>2. When the output of the opamp is high, the mosfet will conduct

It is a P channel, so it is the other way around

So basically, when the voltage gets larger than a certain value, the mosfet turns off.

You'd usually have a cap on the output to smooth the rise/fall time

We have a circuit at my work that has been used since the 90s which uses this technique to regulate the output voltage, and a very similar way to regulate max current.

The opamp in your circuit is in a closed loop configuration. Is that correct?

 

It's working as a comparitor

 

It's working as a comparitor

OK if bang-bang control is what you want, it's not for me to throw stones.

 

>OK if bang-bang control is what you want, it's not for me to throw stones.

lol - I like that description

It needs to have a cap on the output, but it works quite well.

 

>2. When the output of the opamp is high, the mosfet will conduct

It is a P channel, so it is the other way around

So basically, when the voltage gets larger than a certain value, the mosfet turns off.

You'd usually have a cap on the output to smooth the rise/fall time

We have a circuit at my work that has been used since the 90s which uses this technique to regulate the output voltage, and a very similar way to regulate max current.

Ok. So we have targeted my misunderstanding. Thank you both for your speedy and helpful replies.

According to this table:
(from https://www.electronics-tutorials.ws/transistor/tran_7.html)


The mosfet does not conduct when Vg-Vs is greater than zero.

When the opamp output (aka Vg) is high, the voltage Vin (aka Vs) is lower such that Vg-Vs>0 and therefore the mosfet does not conduct.

Thank you!

 

The original circuit has negative feedback due to the phase reversal from the MOSFET which will allow the circuit to regulate the output voltage to Vref times the attenuation from resistors R1 and R2.
But it will require some added compensation because the of the added MOSFET gain to the loop which will likely cause instability if not compensated.

 

It needs to have a cap on the output, but it works quite well.

I suppose that might qualify as "compensation", but a comparator just doesn't seem like the right component for the job. Something like a gain stage with a limiter would be more like it. How does this scheme work with load transients?

 

>How does this scheme work with load transients?

It only has one type load - Its purpose is a CC-CV charger for a very specific battery.

This is also only one part of the circuit - When you see how the current limiting is done, the choice of circuit makes sense.

Unfortunately I can't be sharing my company's IP, but it is a nice way of doing it - It has literally been used for decades.