Hello!
I need some help with following code.
What types of digital circuits, these:
I guess it's some type of encoder in the first case and counter in the second one. I try to find more information on the web but I can't.
Any information or clue is welcome.

1. architecture rtl of D2a is
begin
process (X0, X1, X2)
begin
case (X0 & X1 & X2) is
when "100" => z <= '1';
when "010" => z <= '1';
when "001" => z <= '1';
when "101" => z <= '1';
when others => z <= '0';
end case;
end process;
end D2a;

2.entity asc is
generic (CS : integer := 8)
port (k, ars, srs, e, u: in std_logic;
r: buffer std_logic_vector(Cs-1 downto 0));
end asc;
architecture arch of asc is
begin
p1: process (ars, k) begin
if ars = ‘1’ then
r <= (others => ‘0’);
elsif (k’event and k=’1’) then
if srs=’1’ then
r <= (others) => ‘0’);
elsif (e = ‘1’ and u = ‘1’) then
r <= r + 1;
elsif (e = ‘1’ and u = ‘0’) then
r <= r - 1;
else
r <= r;
end if;
end if;
end process;
end arch;

 

the first one is equivalent to the following boolean equation :
Z = X1*(X0+X2)+X0*X1*X2 (I underlined the inversion since I can't overline)
It looks like some decoder for a display or something like this.

2.entity asc is
   generic (CS : integer := 8)
   port (k, ars, srs, e, u: in std_logic; r: buffer std_logic_vector(Cs-1 downto 0));
end asc;

architecture arch of asc is
begin
  p1: process (ars, k) begin
    if ars = ‘1’ then
      r <= (others => ‘0’);
    elsif (k’event and k=’1’) then
      if srs=’1’ then
        r <= (others) => ‘0’);
      elsif (e = ‘1’ and u = ‘1’) then
        r <= r + 1;
      elsif (e = ‘1’ and u = ‘0’) then
        r <= r - 1;
      else
        r <= r;
      end if;
    end if;
end process;
end arch;

This is a up/down counter. The ports do :
ars : asynchronous reset
srs : sysnchronous reset
e : count enable
u : count up
k : clock
r : 8 bit output vector

Hope this helps.

 

Have read a bit more about digital circuits and VHDL last days.
As I understand the code in the first case could be som type of checker
which determines if the input values represents even or odd value.

is this possible????

architecture rtl of D2a is
begin
process (X0, X1, X2)
begin
case (X0 & X1 & X2) is
when "100" => z <= '1';
when "010" => z <= '1';
when "001" => z <= '1';
when "101" => z <= '1';
when others => z <= '0';
end case;
end process;
end D2a;

 

No. if it would be looking for odd values it would simply check the LSB. These are 3 different signals I'd say, if it represented a value it would be quite strange to decompose the bus in three different threads instead of a 3 bit vector. If you can't provide a clearer context I don't think I can help you further. I'm also quite puzzled by the name of the process : D2a... the only thing that springs to my mind is digital to analog, but that's not it. Decimal to something maybe.