Hi every one,

I have a project do design a circuit for university.
In the circuit I have two binary counter. the first one run on 7.3 Hz and the seconded one on 1 Hz. also the first one make the second one work when he finish counting so they need to be synchronized. I like to know what is the bast way to build a clock which make them work as I said.

thank u so much for your help

 

You could make a 730Hz clock and divide that by 100 for the 7.3Hz clock, and by 730 for the 1Hz clock.

 

The "best" ("best" is in quotes because it really depends on what is important) is to send a single clock signal to every sequential chip in the circuit and then use logic to make the various chips sensitive to some of the clock edges and not to others. Don't gate the clocks - there are demons in those waters. In particular, gated clocks are notorious for generating glitches that the sequential chips will respond to unless the design is very carefully done.

EDIT: Fixed typo.

 

You could make a 730Hz clock and divide that by 100 for the 7.3Hz clock, and by 730 for the 1Hz clock.

I was thinking to divide the frequency using monostable. is that make sense?

 

I was thinking to divide the frequency using monostable. is that make sense?

Not if you want a reliable divide ratio.
It's generally best to do a frequency divide with digital circuits, not analog.

 

Basic ways of synchronizing digital circuits -

https://vlsiuniverse.blogspot.com/2013/09/synchronization-schemes.html

http://www-inst.eecs.berkeley.edu/~cs150/sp12/agenda/lec/lec16-synch.pdf


Regards, Dana.

 

He wants the clocks in the two domains to be synchronized. If they are unsynchronized and use the double-register technique, then there will be times that a signal is registered on the wrong clock. When dealing with truly unsynchronized domains, that's just a reality that you have to accept. But it sounds like here the behavior is predicated on the assumption that the two domains are synchronized.