Hello all,

I have a circuit that employs a 74LS08 AND IC as a digital signal switch. Each of the four gates has a square wave ( different frequencies) on one pin and a PIC micro output on the other pin (enable). The outputs from all of the gates are tied through a capacitor to the gate of a transistor configured as an emitter follower (I need to source more current than the IC can provide). The outputs are enabled sequentially from lowest frequency to highest and are never on at the same time. I have found that there is significant attenuation of the signals at the outputs. I configured a quad 2 input OR gate as a 4 input OR gate to multiplex the signals, which worked great, but I need to maintain the amplitude of the individual signals at different levels. I'm going buffer each of the outputs with transistors to solve the problem, but I would like to understand why the signals are attenuated so much with the outputs tied together. Can anyone help?

 

A quick note. I know this is due to "gate fighting". I would like understand how this occurs.

 

Schematic schematic schematic. The description of your problem is not clear. However, gate fighting is. A standard TTL gate has two output transistors. One tries to pull the load up to 5 V (high), and the other tries to pull it to GND (low). When you tie two TTL outputs together, there is the possibility that one output will be high and the other one low, creating a pseudo-dead-short through the two output stages. This can cause device failure.

ak

 

Off the wall suggestion: you could use a 74LS01 instead of the '08. These gates are open collector output so you need a pull-up resistor, but you can connect all the outputs in parallel quite properly.
However:
1. They have different pinouts.
2. They are NAND gates so the clock signals will be inverted - does that matter?
3. If you are using them with fast signals, you will need to check the rise time with the selected pull-up resistor value.

 

Schematic schematic schematic. The description of your problem is not clear. However, gate fighting is. A standard TTL gate has two output transistors. One tries to pull the load up to 5 V (high), and the other tries to pull it to GND (low). When you tie two TTL outputs together, there is the possibility that one output will be high and the other one low, creating a pseudo-dead-short through the two output stages. This can cause device failure.

ak

ALL of that plus LSTTL doesn't actually source very much current - 400uA at 3.4V typical per output compared to 8mA when it sinks. TTL totem-pole outputs are not intended to be paralleled. The accepted method is to do the logic down to one output and use that one to sink if 8mA is enough or drive a buffer like a transistor or ULN2803.

 

Depending on the load, no TTL gate will swing rail-to-rail. It is known.

 

"The outputs from all of the gates are tied through a capacitor to the gate of a transistor" - outputs are connected together and feed a single capacitor? If so, as has been said, you can't do that.

The only time logic outputs can be connected one to another are "open-collector" (or open-drain) or tri-stated outputs.

On the face of it you have 1 output pulling high vs. 3 pulling low, I am surprised you have any output.

You could use a data selector -- LS151 or CMOS 4512 with the advantage of requiring only 3 PIC lines if such things are still available

 

Schematic schematic schematic. The description of your problem is not clear. However, gate fighting is. A standard TTL gate has two output transistors. One tries to pull the load up to 5 V (high), and the other tries to pull it to GND (low). When you tie two TTL outputs together, there is the possibility that one output will be high and the other one low, creating a pseudo-dead-short through the two output stages. This can cause device failure.

ak

I love it! AnalogKid with digital answers! Thanks for your response. That explains exactly what I wanted to understand.

This is a project I have been working on for quite some time. It is a circuit that produces short noise events. I am designing it to test a CISPR 14 discontinuous interference analyzer system. I'm using Schmitt trigger inverters to produce signals at 150 kHz, 500 kHz, 1.4 MHz and a shielded crystal oscillator for the 30 MHz signal. I'm switching each of the frequencies and intervals of 8ms, 17ms, and 25ms with a 10s pause between each interval. I'm using a PIC 12F629 micro to enable each of the logic gates for the given intervals. Then I need to drive those signals onto the hot and neutral lines of a live 120 Vac, 60 Hz power cord through a pair of X-caps. Its difficult to upload the schematic because its kind of large and I have it drawn in a hierarchical system. I'll post the finished project in the Projects Forum soon. Thanks again for sharing your knowledge.

Off the wall suggestion: you could use a 74LS01 instead of the '08. These gates are open collector output so you need a pull-up resistor, but you can connect all the outputs in parallel quite properly.
However:
1. They have different pinouts.
2. They are NAND gates so the clock signals will be inverted - does that matter?
3. If you are using them with fast signals, you will need to check the rise time with the selected pull-up resistor value.

Albert, thanks for the tip. I found the same answer last night after doing some more research. I just happen to have some 74LS01 ICs laying around. This will be much easier that having to stuff transistor buffers into the circuit.

Thanks to all that responded. This site is a great place to get tips and advice.

Bill