Trying to figure out LVCMOS Interface - Will this work?

Thread Starter

matthej

Joined Oct 10, 2020
10
Hi,

I am trying to see if this interface will work. I am worried about the Vol to Vih relationship as there is no margin. The vendor of the driver thinks it will be ok. Here are the parameters:

Driver: Voh=2.3V (min), Vol=0.8V(max)
Receiver: Vih=2.0V(min), Vil=0.8V(max)

So as you can see there is no margin when driving low. My questions:

1) Is this ok? Won't any noise cause it to go to an unknown logic area?
2) Is there something I can do to bring down Voh? A pulldown?
3) Will the driver ever be able to drive 0.8V when in the low state? Does it depend on Iol and Iil?

Thanks!
 

andrewmm

Joined Feb 25, 2011
671
what chip are you using for the driver that has such a bad Vol ?
as you suspect , at best that is a very marginal interface,

what speed you trying to drive at ?
 

Thread Starter

matthej

Joined Oct 10, 2020
10
what chip are you using for the driver that has such a bad Vol ?
as you suspect , at best that is a very marginal interface,

Its a DAC from Teledyne E2V - the signals in question are STVF and HTVF flags.

what speed you trying to drive at ?
I am not sure the speed since they only will be toggled if there is a setup or hold time violation.

I have attached the datasheet as well
 

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Thread Starter

matthej

Joined Oct 10, 2020
10
What makes you think that? They look compatible to me.
If there is any noise on the line and the Vol goes to 0.9V (for example) how would that be interpreted on the input since its expecting a Vil of 0.8V maximum. Wouldn't that be in the undefined region of the device?
 

dl324

Joined Mar 30, 2015
11,914
If there is any noise on the line and the Vol goes to 0.9V (for example) how would that be interpreted on the input since its expecting a Vil of 0.8V maximum. Wouldn't that be in the undefined region of the device?
You're looking at the worst case specs. The only way it could be a problem is if you had a noisy environment *and* a worst case part. Most parts are going to be closer to typical and they should have given you a value for typical (e.g. most) devices.
 

Thread Starter

matthej

Joined Oct 10, 2020
10
You're looking at the worst case specs. The only way it could be a problem is if you had a noisy environment *and* a worst case part. Most parts are going to be closer to typical and they should have given you a value for typical (e.g. most) devices.
Understood. Is there anyway to determine what the max Vol will really be based on the load? If I knew the input low current level, could I figure this out?
 

Thread Starter

matthej

Joined Oct 10, 2020
10
How is the driver loaded? The output voltage will depend on loading. A lightly loaded output will have a Voh higher or a Vol lower than the worst case specs.
The driver is driving one of these LVCMOS Xilinx loads as noted above. The datasheet does not list the input current requirements, just the open ones. Is that what you are looking for?
 

andrewmm

Joined Feb 25, 2011
671
Oh I do love E2V chips,
I know them well, seems they never seem to be designed for real world usage.
e.g. How hard is it to make a standard CMOS output that makes the normal Vol of 0.4 v ..
there is even a note in the data sheet to use resistors to correct this ,,,

As others have said, its only the worse case scenario and when you have noise that problems occurs, but as this is a very expensive and not very good DAC, I'm guessing something that works "most the time" is not what your after.

( I once had a design that used one of the E2V chips, and even the reference design and FPGA did not work reliably ,,, )

So, what to do,
a pull down on the line will lower the Vol , at the expense of the VoH numbers,

The other question, is are what is the timing on these signals.
Are they just spikes when the misalignment occurs, or "mono stable" flags that stay high / low while the condition occur, can the flags over lap,
If they are decent pulses, what is the timing, can you register them into the FPGA , or are you expected to integrate the pulses to make a level ?

I'd push Teledyne strongly to get there proven reference circuit and code, if they can not provide it, then I'd doubt if its really possible to use.

My thought is they are going to be slow / wide signals, and maybe you could use an external comparator to make a decent signal,,

alternatively, look at the analog devices range, much better thought out interfaces and performance IMHO.
 

dl324

Joined Mar 30, 2015
11,914
The driver is driving one of these LVCMOS Xilinx loads as noted above. The datasheet does not list the input current requirements, just the open ones. Is that what you are looking for?
The worst case specs are for driving maximum fanout load. I recall that being 20. For a single load, specs won't be worst case.
 

andrewmm

Joined Feb 25, 2011
671
Output voltage levels are lowered by a load to ground,
so an extra resistance to ground, will lower VoL and VoH,
as you seem to have plenty of VoH, a load to ground would seem to be the way forward.

Find out what the IoH of the driver is,
that will dictate how low a resistance to ground you can use,
my gut thought would be about 470 Ohms,
 

Thread Starter

matthej

Joined Oct 10, 2020
10
Output voltage levels are lowered by a load to ground,
so an extra resistance to ground, will lower VoL and VoH,
as you seem to have plenty of VoH, a load to ground would seem to be the way forward.

Find out what the IoH of the driver is,
that will dictate how low a resistance to ground you can use,
my gut thought would be about 470 Ohms,
so the output Ioh and Iol are 80uA for each one. How would you determine what resistor to ground you would need?
 

andrewmm

Joined Feb 25, 2011
671
Are you certain on the units ?
at 80 uA, I doubt you can even drive a logic "1" with a single load, let alone adding a resistor.

Id expect most sensible logic to be at least 2 mA, normally 16mA or above Ioh
 

Thread Starter

matthej

Joined Oct 10, 2020
10
Are you certain on the units ?
at 80 uA, I doubt you can even drive a logic "1" with a single load, let alone adding a resistor.

Id expect most sensible logic to be at least 2 mA, normally 16mA or above Ioh
This is directly from the datasheet. I was surprised as well, although it could be a typo as I have found a few...

The note 6 next to it says source or sink

Capture.PNG
 

andrewmm

Joined Feb 25, 2011
671
Well, that is un usable, that is not enough to even drive one LVCMOS input,

A typical E2V data sheet / part IMHO.


Its wait till monday and get onto the E2V help line,
sorry
 

andrewmm

Joined Feb 25, 2011
671
Agreed,
But the real PCB has capacitance / inductance, as well as the resistance and capacitance of the pins at both ends.
the drive current has to charge / discharge these ,

You also have to overcome the interference induced in the line by external environment,

Good luck with 80 uA drive current,
 
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