# trouble calculating circuit delay

Joined Apr 4, 2017
10
concerning the attached circuit:
the table describes the proper delays of each piece of the circuit (except D)
D is a delaying component made of an even number of inverters (NOTS)
it's given that for every 'm' - number of inverters the following is applies:

tpd(D)=3m
tcd(D)=2m

CL is some combinational logic with delays according to the table.
clock time is 42ns

what is the maximum number of inverters in D that will keep the circuit functioning properly?

what I got is:

T(hold) considerations:

min{(tcd(D)+tcd(FF2)+tcd(D)),tcd(FF1)}+tcd(CL)>=Thold(FF2)+tpd(D)

I checked th minimum, and it goes:
4m+3<5
m<0.5
meaning there is no number of inverters that will satisfy this condition, therefore
5+tcd(CL)>=Thold+tpd(D)
12>=1+3m
11/3>m
3>=m

T(setup) (clock time) considerations:
this is referring to the lower D
tpd(FF1)+tpd(CL)+tpd(FF2)+tpd(D)<= t(clock)+tcd(D)
this is referring to the upper D
14+15+16+3m<=42+2m

m<=-3
meaning the circuit will not function properly anyway

where did I go wrong and what is the proper calculation?