Hello,
I tried design a D-latch as in the attachment and I've always been asked by my lecturer what is the switching time for the transmission gate. from what I understand is that both of the transmission gate were provided with the same clock so it should have the same switching time or is there some cases one of the transmission gate is provided with different clock source?

Another question is when designing a flip-flop, most of the module that I learned in university always talk about the setup and hold time "definition" but lack of explanation of how both violations are actually determined when designing a flip-flop. It could very useful if anyone can explain this.

Thank you.

 

Hello,
I tried design a D-latch as in the attachment and I've always been asked by my lecturer what is the switching time for the transmission gate. from what I understand is that both of the transmission gate were provided with the same clock so it should have the same switching time or is there some cases one of the transmission gate is provided with different clock source?

Another question is when designing a flip-flop, most of the module that I learned in university always talk about the setup and hold time "definition" but lack of explanation of how both violations are actually determined when designing a flip-flop. It could very useful if anyone can explain this.

Thank you.

I'm not sure what your question on "set up" and "hold" times are. Set up is a question of how long the data inputs must be stable before the clock pulse happens. Hold time is how long the clock pulse must be to assure complete success of the operation.
"Switching time for the transmission gates" How long does it take for the transmission gates to operate after the leading edge of the clock pulse? I don't know how you would determine that since you don't control the design of the transmission gate. Is it specified in the simulation model?

 

I'm not sure what your question on "set up" and "hold" times are. Set up is a question of how long the data inputs must be stable before the clock pulse happens. Hold time is how long the clock pulse must be to assure complete success of the operation.
"Switching time for the transmission gates" How long does it take for the transmission gates to operate after the leading edge of the clock pulse? I don't know how you would determine that since you don't control the design of the transmission gate. Is it specified in the simulation model?

thank you for your opinion

I know about the set up and hold time are, how do we actually know the time frame of set up time let's say 20ns and hold time 30ns. Is it just a random numbers that we set for both violations or simulation has to be done first to determine the value for both violations.

for the transmission gates, I also have no idea what did my lecturer want. But this is my thought, it should be the same as the time taken for the transistor to reach saturation because from what I learned in cmos inverter switching happens when both PMOS and NMOS are at saturation region

 

thank you for your opinion

I know about the set up and hold time are, how do we actually know the time frame of set up time let's say 20ns and hold time 30ns. Is it just a random numbers that we set for both violations or simulation has to be done first to determine the value for both violations.

for the transmission gates, I also have no idea what did my lecturer want. But this is my thought, it should be the same as the time taken for the transistor to reach saturation because from what I learned in cmos inverter switching happens when both PMOS and NMOS are at saturation region

I imagine hold times would depend on the sum of the transition times of the gates. same for setup time.