Creation of a CMOS Transmission Gate in LTSPice

Thread Starter

BigEWVU

Joined Jul 14, 2019
2
When creating a transmission gate in LTSPice, what is the difference between using a NMOS4 and PMOS4 (monolithic w/ substrate connection) versus an NMOS and PMOS with G S D connections? Will there be any complications when using this transmission gate in the creation of other devices such as a D Flip-Flop or master-slave D Flip-Flop?

Thank you
 
Last edited:

dl324

Joined Mar 30, 2015
8,954
Welcome to AAC!

Four terminal MOSFETs aren't readily available, so it's more of an exercise in theory. If you have access to the bulk connection of a MOSFET, you can adjust body bias.

To make transmission gates or D FF, you don't need an explicit substrate connection for typical designs.
 

WBahn

Joined Mar 31, 2012
24,700
When creating a transmission gate in LTSPice, what is the difference between using a NMOS4 and PMOS4 (monolithic w/ substrate connection) versus an NMOS and PMOS with G S D connections? Will there be any complications when using this transmission gate in the creation of other devices such as a D Flip-Flop or master-slave D Flip-Flop?

Thank you
If you are using discrete components, you almost certainly will not have access to the bulk (body) connection as a separate connection -- it will be internally tied to the source node. But if you are simulating an integrated circuit, then the bulk connection is not intrinsically tied to the source. For instance, in an NWELL processes the bulk of the NFETs is the substrate while the source/drain may both be connected to something other than the substrate, while the bulk of the PFETs is tied to the well that they are in and you can do with that what you want -- including injecting a signal into it.
 

dl324

Joined Mar 30, 2015
8,954
I think in some NWELL processes, they use guard rings to make pseudo-isolated substrate regions. At least that's my recollection from discussions I had with colleagues.
 

ci139

Joined Jul 11, 2016
725
use R=functionof(V.supply,V.control) and you'll avoid simulation hanging up or being too slow
smth. like
*Pass-Gate Gnd Ctrl Inp Outp Vss
.SUBCKT P-Gate 1 2 3 4 5
R0 3 4 R = .1G * u( V(5,2) - V(2,1) ) + log(20-V(5,1)) / log(2) * 150
.ENDS
fast test of the above :
pRAM - Test - b11.png
 
Last edited:

WBahn

Joined Mar 31, 2012
24,700
I think in some NWELL processes, they use guard rings to make pseudo-isolated substrate regions. At least that's my recollection from discussions I had with colleagues.
Guard rings don't change the fact that the bulk connection is still tied to the substrate. The idea with a guard ring is that the current flowing in the bulk connection of one transistor is picked up by the guard ring connection instead of being seen by other nearby NFETs. It's a crosstalk issue (and also a latch-up issue), but the bulk is still tied to the substrate even if the source is not.
 

WBahn

Joined Mar 31, 2012
24,700
use R=functionof(V.supply,V.control) and you'll avoid simulation hanging up or being too slow
smth. like
*Pass-Gate Gnd Ctrl Inp Outp Vss
.SUBCKT P-Gate 1 2 3 4 5
R0 3 4 R = .1G * u( V(5,2) - V(2,1) ) + log(20-V(5,1)) / log(2) * 150
.ENDS
How does this relate to the question asked by the TS?
 

dl324

Joined Mar 30, 2015
8,954
Guard rings don't change the fact that the bulk connection is still tied to the substrate. The idea with a guard ring is that the current flowing in the bulk connection of one transistor is picked up by the guard ring connection instead of being seen by other nearby NFETs. It's a crosstalk issue (and also a latch-up issue), but the bulk is still tied to the substrate even if the source is not.
That's why I said pseudo isolated. I never worked on any designs that used that "feature", but I recalled colleagues who did talking about it. I never paid much attention because I worked on products that didn't have to fiddle with body bias because the process included enough threshold voltages without having to resort to body biasing.
 

ci139

Joined Jul 11, 2016
725
... creating a transmission gate in LTSPice ...
using whatsoever mosfets is not very good idea (unless you want to make a short interval or not too events dense simulation to investigate the single gate operation in particular)
... Will there be any complications when using this transmission gate in the creation of other dev ...
you bet!

How does this relate to the question asked by the TS?
? it's in the same thread ? o_O
 

WBahn

Joined Mar 31, 2012
24,700
That's why I said pseudo isolated. I never worked on any designs that used that "feature", but I recalled colleagues who did talking about it. I never paid much attention because I worked on products that didn't have to fiddle with body bias because the process included enough threshold voltages without having to resort to body biasing.
Very few designs ever intentionally use body biasing. The problem is that since the bulk is not connected to the source, every NFET transistor in the circuit that does not have it's source tied to the substrate (which is most of them) WILL have a body bias on it. So if you are designing noise-sensitive circuits, you need to take that into account -- or at least use transistor models in your simulations that take it into account. Also, since you do have the option of tying your PFET bodies to their respective sources, you can design your circuit so that portions that are particularly sensitive to bulk-bias modulation are implemented in PFETs -- though this requires that each PFET be in its own well, which can substantially increase the area required for the design (and also reduce the matching of your PFETs since they are now physically further apart from each other).
 

Thread Starter

BigEWVU

Joined Jul 14, 2019
2
I attached below my current setup and I think everything is working correctly. I am confused why I still get output voltage when the Control voltage (VC) is set to 0V. Shouldn't the circuit be considered open and 0V at the output?
 

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crutschow

Joined Mar 14, 2008
23,366
Where you connect the substrates affects the ON characteristics of a transmission gate.
Connecting them to the fixed bias of ground for the N-MOSFET and V+ for the P-MOSFET will reduce the on-resistance of the transmission gate for the mid voltage signals.
I am confused why I still get output voltage when the Control voltage (VC) is set to 0V. Shouldn't the circuit be considered open and 0V at the output?
You need complementary signals to the gates.
To turn the transmission gate off the N-MOSFET gate should be at ground and the P-MOSFET gate at Vdd.
 

dl324

Joined Mar 30, 2015
8,954
I am confused why I still get output voltage when the Control voltage (VC) is set to 0V. Shouldn't the circuit be considered open and 0V at the output?
Try putting a resistor to ground on the output. Then explain why the result isn't, or is, the same.
 

WBahn

Joined Mar 31, 2012
24,700
I attached below my current setup and I think everything is working correctly. I am confused why I still get output voltage when the Control voltage (VC) is set to 0V. Shouldn't the circuit be considered open and 0V at the output?
You are probably seeing charge-storage effects. Essentially the output of your transmission gate is a DRAM capacitor that you charge to 5 V when the transmission gate is ON and then that voltage is getting stored on the capacitance of the output when the t-gate is OFF. Do this -- put two equal largish resistors (perhaps 10 kΩ) between the positive and negative rails and tied the output of your t-gate to the junction. This will try to passively drive the output to mid voltage. Then ramp your input signal slowly from 0 V to 5 V while turning the t-gate on and off. See if the results make sense.
 
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