Hi all!

I just want to ask how to eliminate the overshoot of my pulse generated by using a comparing vref and ramp. Thanks

 

hi CTD,
Are you you sure that the Clock pulse overshoot and undershoot is not an artefact created by your scope/probe.?
E

 

Its a simulation in TSMC 65nm. not a device.

 

Inductance is everything. Minimize that in your layout.

I am not a chip designer, did a stint as a product engineer, so
take my comment with a grain of salt.

Regards, Dana.

 

Good simulator. In real world we always have these spikes.
Highly likely© they will eliminate by input capacitance of next stage.

 

Why do you consider those small spikes a problem?
They won't affect circuit operation.

 

The timescale on plot telling, those transients might just be much larger when
sampled properly.

Regards, Dana.