well i need some help ,i can't find what is the device packaging constraints of TO5 packaging Flat Pack packaging and the Dual In-Line packaging ,can anyone tell me what's the constrains of that? I am confusing of that, thx so much

 

What do you mean by "constraints?"

 

limit. its mean about what is the bad of that packaging

 

Hi,

Your question is pretty broad. Plus TO-5 transistor cans have been replaces by the TO-39 package, and flat packs lost out to dual inline package many years ago.

Probably the least good feature about dip's is poor heat dissipation. I've stuck on a PDF that gives ic package dimensions, if that helps.

 

thx beenthere,it will help me alot!!

 

erm i can know about the different of there 3 packaging?and compare it ,thanks