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Because of the presence of the L101 inductor the FET source goes about 0.5V negative when the FET turns off. So the bootstrapping should work ok. Simulation with an IR2110 model says it does, and the last scope shot above also show Vs going slightly negative.
TL494/594 Buck converter timebase distorted
- Thread starter Mario74m
- Start date
Great tips, thank you for the time you dedicated to my problem. I’ll be able to work on the project tomorrow afternoon at earliest, meanwhile I double checked with my LTSPICE simulation (attached - it is IR2110 based, since it stalls when I use the IR2117 model that I have). Voltage spikes on VB reach some 51V, which is near your value. I'll check with the IR2110/17 datasheet.
Just to mention - the reason I used IR2110 in non-synchronous configuration was exactly the fact that the LTSPICE simulation showed it would work.
Oh, and I forgot to apologize for my not-so-perfect English language skills - it is not my native tongue.
Nonsense - The IR2117 will stand 600V on Vb. Vb will be 14.5V above Vs, because the bootstrap capacitor is charged from the supply on Vcc.
Oops. My bad. Post #20 edited.
I think Lan0 suggestions should have worked. See below.
Note the 2110 is powered by 15v.
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Ian0's suggestions are working, and eetech's spice simulation results are consistent with my own dating back to the initial design. After replacing the IR2110 with IR2117 the regulator still wasn't working correctly due to bootstrap capacitor not charging - while reworking the pcb to adjust for new pinout, I missed one capacitor pin so it was floating. After I connected it, I get 12V on output, and I'm able to regulate it as designed. Great thanks to anyone who dedicated their time and contributed to the thread so far!
However, some of the waveforms are less then ideal because of large amount of ringing on the Mosfet source and all other voltages that are referenced (or dependent) to it. Here are some scope shots:
MOSFET V_source:
IR2117 IN(ch1)+HO(ch2):
MOSFET V_GS:
An interesting one - scope probe pin in air around the toroidal inductor, with ground clip on PCB GND copper pour:
So, the circuit output is correct, the only thing that kinda worries me is the glitch in the rising edge of the V_GS waveform, but I'm not sure whether to attribute the ringing to the resonant circuit formed by output (low ESR) capacitor and inductor (don't think so, since its resonant frequency is around 600Hz according to calculation, while the ringing frequency seems to be around 150kHz). In that case, maybe a small ohmic resistance in series with the capacitor could help to dampen the oscillations. Or it could be atributted to the stray magnetic flux from the inductor, or the parasitics due to my jumper wires from PCB reworking. Or possibly some other reason?
However, some of the waveforms are less then ideal because of large amount of ringing on the Mosfet source and all other voltages that are referenced (or dependent) to it. Here are some scope shots:
MOSFET V_source:
IR2117 IN(ch1)+HO(ch2):
MOSFET V_GS:
An interesting one - scope probe pin in air around the toroidal inductor, with ground clip on PCB GND copper pour:
So, the circuit output is correct, the only thing that kinda worries me is the glitch in the rising edge of the V_GS waveform, but I'm not sure whether to attribute the ringing to the resonant circuit formed by output (low ESR) capacitor and inductor (don't think so, since its resonant frequency is around 600Hz according to calculation, while the ringing frequency seems to be around 150kHz). In that case, maybe a small ohmic resistance in series with the capacitor could help to dampen the oscillations. Or it could be atributted to the stray magnetic flux from the inductor, or the parasitics due to my jumper wires from PCB reworking. Or possibly some other reason?
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The waveforms look like the converter is in DCM.
Were the waveforms captured with the converter loaded? If so, what was the load?
100 ohm external resistive load (a cement resistor), plus inbuilt 10 kOhm parallel to it (see schematics-but I presume that it is negligable in this context).
Simulation says a ~47n cap between drain and source dampens the oscillation without significantly increasing the FET's dissipation.
Interesting. A Spice simulation of the TS's schematic shows ringing in continuous current mode. I wonder why the difference?
Can you post the waveforms?
Something else might be ringing? The top picture in post #27 is classic discontinuous mode ringing. There is the MOSFET conducting phase, followed by the DIODE CONDUCTING phase, then when the inductor runs out of current, there is nothing left in circuit except the inductor and the MOSFET's drain-source capacitance, with no load resistance - the Q will be huge.
I bet you could make a quasi-resonant converter, by switching the MOSFET back on at the first positive peak of the ringing. There would be very little voltage across it, so much reduced switching losses.. . . but that's another project!
OK, so I tried to calculate the critical current for the CCM-DCM limit according to a TI appnote that I have, and if I'm correct it is 0.313A for my component values, which translates to 38Ohm load. Therefore I cranked up the current by connecting two 10 Ohm 10W cement resistors in parallel and obtained 2.3A at output. The waveforms:
V_source (xN, x1):
V_gate-source:
IR2117 IN pin:
So, occasional glitches on V_GS, but also on the input of the driver, and a bit unstable switching frequency, but the ringing is gone, it would seem?
I must say that it pleases me that all the active components (FETs, ICs and bridge and low-side Schottky diodes) are almost stone cold at this current even without heatsinks, which amounts to some 10-15% of the maximum designed value. The only thing that heats up is the PTC inrush current limiter, but that's inevitable. I ran it only for two minutes, though, to avoid the load resistors to glow, but I think that with heatsinks and (maybe) a fan, the circuit would be able to provide 200W of power without overheating.
V_source (xN, x1):
V_gate-source:
IR2117 IN pin:
So, occasional glitches on V_GS, but also on the input of the driver, and a bit unstable switching frequency, but the ringing is gone, it would seem?
I must say that it pleases me that all the active components (FETs, ICs and bridge and low-side Schottky diodes) are almost stone cold at this current even without heatsinks, which amounts to some 10-15% of the maximum designed value. The only thing that heats up is the PTC inrush current limiter, but that's inevitable. I ran it only for two minutes, though, to avoid the load resistors to glow, but I think that with heatsinks and (maybe) a fan, the circuit would be able to provide 200W of power without overheating.
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Looks like you changed the switching frequency?
You've got the explanation of that odd pulse at the start of the Vgs waveform right there - 2nd picture in post #35. The control IC is suffering form jitter and is sending out a double pulse.
Unfortunately, that's what you get from using an old-as-the-hills IC instead of a modern one.
Double pulses like that are bad for reliability as they increase the switching loss.
The clock doesn't look too stable either!
Unfortunately, that's what you get from using an old-as-the-hills IC instead of a modern one.
Double pulses like that are bad for reliability as they increase the switching loss.
The clock doesn't look too stable either!
Haven't changed the switching frequency, that's the scope measurement subsystem getting confused from all the glitches I suppose.
Curiously enough, the clock seems to be as stable as it could be (it is determined by the R_T / C_T combination on two pins of the TL494). However, the C_T ramp has noise exactly at the points of PWM signal switch-on and off- (caused by the very switching, as it seems from the time sequence), which is enough to cause it to throw a false pulse. Agreeably, this is probably the consequence of internal design of the ancient IC that TL494 is, but it's also a good analysis excercise, at least for me.
I have made some more screenshots in case anyone is still interested.
The TL494 CT ramp/clock signal (ch1) and E1/E2 emitter output/pwm signal (ch2):
The TL494 CT ramp/clock signal (ch1) and E1/E2 emitter output/pwm signal (ch2) - single shots. Here the noise and it's consequence on the PWM signal is clearly visible:
Curiously enough, the clock seems to be as stable as it could be (it is determined by the R_T / C_T combination on two pins of the TL494). However, the C_T ramp has noise exactly at the points of PWM signal switch-on and off- (caused by the very switching, as it seems from the time sequence), which is enough to cause it to throw a false pulse. Agreeably, this is probably the consequence of internal design of the ancient IC that TL494 is, but it's also a good analysis excercise, at least for me.
I have made some more screenshots in case anyone is still interested.
The TL494 CT ramp/clock signal (ch1) and E1/E2 emitter output/pwm signal (ch2):
The TL494 CT ramp/clock signal (ch1) and E1/E2 emitter output/pwm signal (ch2) - single shots. Here the noise and it's consequence on the PWM signal is clearly visible:
Can you post the schematic that the screen shots represent?
I'd like to simulate it and see how closely they match.
Have a real good look at the 0V connections around the control IC. Make sure that they all go to a single point, which the joins to the power ground by one track.
Also check that the interference isn’t on the 15V supply. 7815s don’t have the best PSRR at high frequency!
Also check that the interference isn’t on the 15V supply. 7815s don’t have the best PSRR at high frequency!
