I'm trying to understand the derivation of the equation for the minimum delay of a sequential circuit to work properly and prevent metastability.

In our class, it is given as

min time \( = T_h - T_{clktoq} \)

min time = (holding time of destination flip-flop) - (time it takes for the source flip flop's output value to actually show up on the output after the rising edge of the clock)

If Th < Tclktoq then minimum time is zero, but why is this the case? Shouldn't the circuit have to wait at least Tclktoq or Th to work? I'm not sure how to understand this equation. Also in the case there is no source flip flop, it would be just holding time then?

 

You haven't been very careful about defining what your "min time" is. It's not enough to say that it is the "minimum delay of a sequential circuit" because there are many peices of a sequential that you can measure the delay of.

From reading between the lines, I think you are finding the minimum allowable delay from the output of one flip flop to the input of another. Does that sound correct?

Let's assume that it is.

Okay, let's make up some numbers. We'll assume that we have a FF that has a minimum hold time of 100ns and a propagation delay from the rising edge of the clock to the output of 30ns. Now, in between the two FFs is some digital logic that uses the output from the first FF, performs some logic on it, and produces the input to the second FF. This is sometimes called "glue logic". Let's say that this glue logic has a propagation delay of 80ns.

So, the clock rises (on both FFs) and 30ns later the output of the first FF changes. Then, 80ns after that, the output of the glue logic changes -- or 110ns after the rising clock edge. Since this is after the 100ns hold time requirement of the second FF, we have no problem.

But now let's say we replace the glue logic with some that is a bit faster. Our new glue logic has a propagation delay of 60ns. Now what happens after the rising clock edge? Once again, 30ns after the clock edge the output of the first FF changes. Then, 60ns the output of the glue logic (the input of the second FF) changes. But this is only 90ns after the rising clock edge and we have a hold-time violation.

So, what is the minimum delay through the glue logic that will ensure that we do not have a hold time violation?

 

From reading between the lines, I think you are finding the minimum allowable delay from the output of one flip flop to the input of another. Does that sound correct?

Let's assume that it is.

Sorry, that is what I meant.

So, what is the minimum delay through the glue logic that will ensure that we do not have a hold time violation?

Minimum delay would 70 ns then?

Thanks, this makes things a lot clearer. I was also confused because I was thinking that the minimum delay between the flip flops couldn't be less than the propagation delay, but we are finding the glue logic delay not the entire path.

 

Sorry, that is what I meant.



Minimum delay would 70 ns then?

Thanks, this makes things a lot clearer. I was also confused because I was thinking that the minimum delay between the flip flops couldn't be less than the propagation delay, but we are finding the glue logic delay not the entire path.

Yes, it will be 70ns, which is consistent with the equation you started with. And hopefully you also see why, if the clock-to-output delay is greater than the hold time, that there is no minimum delay along the path inbetween. This is why most FF families ensure that the maximum hold time is less than the minimum clock-to-output delay since many FF outputs will be directly connected to the inputs of others.