I'm unsure as to how to respond this question. I'm a bit thrown off by the fact that we do not have the register covering out put of the first xor gate on top so I'm not sure how to answer it based on that. But from what I understand,what I did was to calculate the time constrain of the middle register using this formula:Tc ≥ tpcq + tpd + setup, and from then I used the same formula to calculate the Time constrain of the 3rd register and add it to the one of the middle. I'm not sure if that's the right idea. Thanks

Given the circuit in Figure 1, each two-input XOR gate has a propagation delay of 60 ps and a contamination delay of 40 ps. Each flip-flop has a setup time of 60 ps, a hold time of 20 ps, a clock-to-Q propagation delay of 70 ps, and a clock-to-Q contamination delay of 50 ps. (a) If there is no clock skew, what is the maximum operating frequency of the circuit? (b) How much clock skew can the circuit tolerate before it might experience a hold time violation?

 

Describe what is meant by "contamination delay"? I've never heard that term before, but that probably just means that we use a different term here.

 

Describe what is meant by "contamination delay"? I've never heard that term before, but that probably just means that we use a different term here.

Contamination Delay: Minimum time from when an input changes until any output starts to change. Time after clock edge that Q might be unstable (i.e., start changing)

 

If contamination delay involves a time relative to a clock edge, then how can an XOR gate have a contamination delay when it doesn't have a clock!

A sketch showing what the terms that you are using mean might be very helpful.

 

If contamination delay involves a time relative to a clock edge, then how can an XOR gate have a contamination delay when it doesn't have a clock!

A sketch showing what the terms that you are using mean might be very helpful.

Here is an example used in class, hopefully it helps.