Hello everyone!
For the following circuit, I need to write the timing constraints of Tclk & Thold, for routes FF0->FF1 & FF1->FF0.
It's given that the clock pulse arrives to FF1 in a delay of 1ns after arriving to FF0.
That's very confusing me, I know how to write the inequalities for Tclk & Thold without clock skew, but once it's added I'm kind of lost.

Without Skew:
FF0->FF1:
Tclk>=Tpcq(FF0)+2*Tpd(NOT)+Tsetup(FF1)
Thold<=Tccq(FF0)+2*Tcd(NOT)

FF1->FF0:
Tclk>=Tpcq(FF1)+Tpd(NOR)+Tsetup(FF1)
Thold<=Tccq(FF0)+Tcd(NOR)

I need your explanation please for how do I add the clock skew to this inequalities and why.
thank you in advance!

 

You need to consider what Tclk and Thold mean.

Draw a timing diagram for the signals as they proceed around the circuit and determine what has to be true in order for signals to get where they need to go without arriving either too early or too late.

 

You need to consider what Tclk and Thold mean.

Draw a timing diagram for the signals as they proceed around the circuit and determine what has to be true in order for signals to get where they need to go without arriving either too early or too late.

I have a timing diagram in the lecture's slideshow and I have also watched some YouTube videos but I still can't understand it well, especially while my english is not perfect.


Thold inequality with skew is more difficult for me.

 

Any additional help?