The output signal is lowered when coupled to the next amp stage.

MrAl

Joined Jun 17, 2014
9,633
Hi, I have a problem I need to understand. Probably the question will be simple If explained in a simple way, and for this reason I chose this section. Very often it happens that the output voltage of the signal of one amplification stage is lowered once hooked to the next amp stage, even with a coupling capacitor. It often happens to me with discrete components like JFETs or transistors, and a little less with opamps. It is probably a physiological behavior of the signal chain, but I would like to understand why, otherwise I can not carry out some of my projects. Thank you for your contribution!
The short answer is that the input of the second stage has input impedance which acts to load the output of the first stage which has output impedance, and anything in between the two (like a capacitor) will act as part of the first stage output impedance and so the signal getting to the second stage will be lowered because of that too.
So you have three main things to consider:
1. The output impedance (or just output resistance) of the first stage.
2. The input impedance (or just input resistance) of the second stage.
3. The intercircuit coupling component(s) like a capacitor or resistor.
Those are the three main things that affect the signal attenuation between stages in amplifiers.
The higher any or all of these component values are, the amount of the loss of signal will be greater and so less signal amplitude will be seen at the very output of the second stage.
 

Thread Starter

DaniKowa

Joined Sep 23, 2020
216
Sorry about the confusion. If you look at the original ASC sim file I have inverted the op-amps to that the non-inverting input is at the top. That is why your sim is not working. You can accomplish that by moving the op-amp. Press Control-E will mirror it and Control-R will rotate it, and pasting it back at the original position.
Don't worry, it's me I have to learn to look better at the details.

hi D,
No need to be sorry, its a common mistake,;)

What about the Input impedance question for both OPA's.??

E
Currently, I am working with discrete components but the links that have been suggested to me, I am reading them anyway because the problem had it also with Opas. The input impedance is high because it will probably be handled by a J-Fet. I'd say at least 1MOhm. As soon as I finish the circuit I place it for considerations.

dcb is providing you with important guidance.

All amplifiers are not equal. There are two ways to connect the input signal to an op-amp circuit.
You can configure the op-amp with the signal going into the inverting input (-IN) or the non-inverting input (+IN or NI).

The input impedance is different for the two configurations.

Learn how these differ.

https://www.electronics-notes.com/a...rational-amplifier-op-amp/input-impedance.php
I agree, in fact I'm reading it. Thank you!
 
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