I only need to do it once, after Power-on-Reset:

(1) The brute-force way to do this is with 8 pullup resistors and 8 I/O pins.

(2) I can do it with a shift-register, 3 I/O pins and 8 resistors?

(3) How about 9 precision resistors and a single ADC input? (this seems sketchy! ~ error-prone)

Any clever ideas on how to accomplish this task in the most minimal, and inexpensive way?

 

I only need to do it once, after Power-on-Reset:

(1) The brute-force way to do this is with 8 pullup resistors and 8 I/O pins.

(2) I can do it with a shift-register, 3 I/O pins and 8 resistors?

(3) How about 9 precision resistors and a single ADC input? (this seems sketchy! ~ error-prone)

Any clever ideas on how to accomplish this task in the most minimal, and inexpensive way?

The resistor and ADC method is a commonly used one. It is used for keyboard matrices, and for multiple switch arrays needing reduced inputs to an MCU. WIth only eight values needed, the resulting resistance of the switched array can be very clearly distinguishable.

You could also use a GPIO expander like the MCP23S08 which uses SPI and has 8 GPIO lines. This is not as simple and clever in one way but in another it’s very clean.

 

The resistor and ADC method is a commonly used one. It is used for keyboard matrices, and for multiple switch arrays needing reduced inputs to an MCU. WIth only eight values needed, the resulting resistance of the switched array can be very clearly distinguishable.

You could also use a GPIO expander like the MCP23S08 which uses SPI and has 8 GPIO lines. This is not as simple and clever in one way but in another it’s very clean.

But isn't it actually 256 values? a bit of a stretch for super reliable?

 

Hi @Sensacell
IF you could have 2, ADC pins available, Read High & Low Nibbles, that would expand the sample limits.
E

 

8 to 3 Line Encoder. I wager this could work with 12 diodes.

 

(2) I can do it with a shift-register, 3 I/O pins and 8 resistors?

That sounds good to me.
You could use an 8-bit, parallel-load SR such as the 74HC165.
It would require just two I/O pins, a clock and serial input.
The parallel-load of the DIP switch positions into the SR could be done by the power-on reset.

 

That sounds good to me.
You could use an 8-bit, parallel-load SR such as the 74HC165.
It would require just two I/O pins, a clock and serial input.
The parallel-load of the DIP switch positions into the SR could be done by the power-on reset.

I think that's the best plan. You could bit-bang the needed signals and use the pins for something else (compatible with the SR connections like LED indicators) after reading the DIP switch.

 

It is cutting it close to get 8 bits resolution. It would be about 100Ω difference between configurations with 100, 220, 470, 1000, 2200, 4700, 10000, 22000 as the 8 values, but of course the more switches on the smaller the effect that 100Ω has on the input voltage the ADC has to sense.

For this many bits it is probably not a good method.

 

If you have 8 port bits that are normaly used as output you could connect them via reasonably high value resistors to the switch and have high value resistors pull up or down resistors. At startup you could set them as inputs, read the post bits then set them back as output for their normal use.

Les.

 

It is cutting it close to get 8 bits resolution. It would be about 100Ω difference between configurations with 100, 220, 470, 1000, 2200, 4700, 10000, 22000 as the 8 values, but of course the more switches on the smaller the effect that 100Ω has on the input voltage the ADC has to sense.

For this many bits it is probably not a good method.

But if you can stretch to TWO A/D inputs, then it's only 4 bits on each.

 

But if you can stretch to TWO A/D inputs, then it's only 4 bits on each.

Yes, a very good suggestion by Eric, above. It would almost certainly work just fine. Or, if you don’t have two ADC, perhaps an ADC and a GPIO with a switch to select which group of bits you are reading via the GPIO pin.

 

Yes, a very good suggestion by Eric, above. It would almost certainly work just fine. Or, if you don’t have two ADC, perhaps an ADC and a GPIO with a switch to select which group of bits you are reading via the GPIO pin.

Apologies to @ericgibbs - I thought I'd read the entire thread.

 

I would verify the CD4094. It might be good for what you intend.

 

Apologies to @ericgibbs - I thought I'd read the entire thread.

A good suggestion is a good suggestion—even the second time.

 

I would go with an 8-line to 3-line binary encoder, 74LS148 or 74HC148.

 

Use a 4051 to multiplex all the switches to one input. You need 3 outputs, but only one pullup resistor.

 

Wow! thank all who have contributed to this interesting problem!

Working through the shift register idea conceptually:
Two ways I could see this working, one is to load the switch states into the shift register as a parallel word, then clock the data into an IO pin, one bit at a time.
The second would be to clock-in a "1" in the LSB, then clock this OUTPUT through the switches, the other side of the switches would then be diode-OR connected to one input pin.

Scenario 1 needs:
Shift register
8 pullups
2 or 3 IO pins (2 if the POR signal can load the register) LOAD, CLOCK, INPUT

Scenario 2 needs:
Shift register
8 Diodes
1 or O pullups (use IO pin internal pullup?)
3 IO pins, CLOCK, DATA, INPUT.

The idea of using 2 analog IO pins, each reading 4 switches is very interesting, as clearly it would be the lowest cost, smallest footprint idea.
What is the clever way to do the resistor network for 4 bits? 16 voltage values?
R-2R ladder? what would that look like?

 

Hi Sensa,
This link shows the method.

E
https://www.electronics-tutorials.ws/combination/r-2r-dac.html

 

Hi Sensa,
This link shows the method.

E
https://www.electronics-tutorials.ws/combination/r-2r-dac.html

I need to think about this a bit, the tutorial assumes the logic inputs are solid logic levels, 0V or Vcc
This would not be the case with the DIP switch, the inputs would either be LOW, or HIGH Z. (floating) or the reverse, Vcc or floating.

My gut tells me this is problematic, some mental chewing is required.

 

This would not be the case with the DIP switch, the inputs would either be LOW, or HIGH Z. (floating) or the reverse, Vcc or floating.

That is a problem.

Below is a sim of a simple ladder network that uses SPST switches, which may work for you:
The steps are compressed towards the top, but should be detectable with an A/D converter.
If the output would go to a trans-conductance (current-voltage) op amp circuit, then the output steps would be equal.
(The glitches are from the CD4024 overlap between states).

If you have a higher voltage source available, then using that for the switch source would, of course, increase the voltage step values.