Hi, need some help understanding this circuit...

So...im trying to figure out how the LEDs and NANDs connect to the RBI of the driver....i think the last NAND is supposed to always output 0/low when the test probe is either 1 or 0 so that the display will work....
But, if the test probe is 0, wont it feed 0 into the last NAND and then make the input of the RBI 1 then?

Greatly appreciate responses

 

Hello,

Have a look at my logic probe:
Project: TTL Logic probe.
It will show symbolic High,Low and pulsating signals.

Bertus

 

Hello,

Have a look at my logic probe:
Project: TTL Logic probe.
It will show symbolic High,Low and pulsating signals.

Bertus

Oh cool
But its really different from the above circuit since it drives the leds of the 7segment individually?

 

Oh cool
But its really different from the above circuit since it drives the leds of the 7segment individually?

When the logic input is HIGH, the display would show a "1" and a "0" when the input is LOW.
The Green LED would indicate LOW and Red LED indicate HIGH.
RBI and RBO are always High when there is valid logic or else the display will be off.

But there is a problem in the circuit. When the input is High the red LED and 7SEG display are correct. When the input is Low, the 7 seg display is OK but the green LED is not lighted. See the sim below.


The input at pin 5 of U2B is not a valid logic low so the out of U2B is also invalid. If you change the NAND gate to a CMOS NAND, then it should work.

Allen

 

One more problem is that the probe doesn't detect pulses e.g. by flashing both LED. SO I think this is a poor design.

Use the design by Bertus instead.

Allen

 

What's the point of having a logic probe that has both LEDs and a 7 segment display to display HIGH or LOW??

Or having one that only works for 5V TTL?

 

What's the point of having a logic probe that has both LEDs and a 7 segment display to display HIGH or LOW??

Or having one that only works for 5V TTL?

I'd go for a CMOS counter and a row of LEDs - if the pulses are faster than persistence of vision, an LED will blink further down the chain. A buffered LED par at the probe tip shows the state of continuous logic level.

Extreme narrow pulses will look static level at the input - but will toggle visibly further along the divider chain.

 

I'd go for a CMOS counter and a row of LEDs - if the pulses are faster than persistence of vision,

I'd opt for a couple inverters to indicate HI/LO and a non-retriggerable one shot to make short or fast pulses more visible.

 

Hi, thanks for the advice

When i simulated it in livewire though..the green led lit up.

Also im avoiding cmos not cuz i want to, but because its not available here. (Phil..stock is 80s level stuff, rare for hobbyist level electronics)

Also, the NAND doesnt have to feed a 0/low into the RBI?

 

When i simulated it in livewire though..the green led lit up.

It's still a bad design.

To turn on the green LED to indicate logic LOW, the 180 ohm current limit resistor would imply that the circuit expected to get about 15mA. LS00 isn't spec'ed to source more than 0.4mA, and that current would need to be sunk by the net being probed.

Similarly, to turn on the red LED to indicate logic HIGH, the 220 ohm current limit resistor would imply that the circuit expected to sink about the same current. LS00 is spec'ed to sink up to 8mA, and that current would need to be sourced by the net being probed.

A better design wouldn't load the net being probed.