Sorry, afraid I can't.I did an lt spice sim here, where I have 2 lines in parallel, and series termination. you said this becomes ratty, but my simulation is fine. you simply forgot to correct the series resistor value... agree?
You picked the pathological case of the two lines being exactly equal length (being driven exactly in the middle of a single line).
Here's what happens when they aren't (which would likely be the real condition):
Yellow traces are for equal length (your simulation), green traces are for T2 being 2/3rds the electrical length (33.3ns) of T1 (50ns).
The signal rather ping-pongs between the two unterminated ends.
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