avoiding truncation of the last A1 pulse during the A2 period is easy. Not so much avoiding truncation of the first A1 pulse. @electronice123, is it acceptable to not enable the first A1 pulse until the entire pulse occurs within the A2 period? In other words, if A1 is already active when A2 goes high, is it OK to ignore it? (A1)

 

Lestraveled, I agree with you, but maybe a simpler approach would be to have the TS describe what he is doing and why he needs this logic filter. There might be a very obvious and easy solution that everyone knows but also knows it doesn't satisfy the constraints as currently understood.

John

 

...................In other words, if A1 is already active when A2 goes high, is it OK to ignore it? (A1)

You would have to ignore it to meet the requirement,"but in a way that does not change the pulse length of any of the shorter pulses."

 

You would have to ignore it to meet the requirement,"but in a way that does not change the pulse length of any of the shorter pulses."

Yes/no. You have two choices here, either ignore it, or find a way to enable the entire pulse. The former is easy, the latter is more complicated.

 

Sorry

Here is a hint.
You will put your A1 signal to one input of a AND gate. The other input will be a gate that is synchronous to A1 yet is triggered by a combination of A1 and A2. The goal is to generate that gate that will turn A1 on and off at the right time. What is the logic condition that you would start this gate and what logic condition would you stop it.

So are you saying to put A1 through one input of the AND gate and A2 through the other, then on a second AND gate the combination of A1 and A2 on one input and A1 on the other?

Give me a few minutes to get my twins down for a nap, maybe then I'll be able to think...

 

.....So are you saying to put A1 through one input of the AND gate and A2 through the other, then on a second AND gate the combination of A1 and A2 on one input and A1 on the other?

Nope.

Your job is to make a enable gate that will let the A1 signal through a AND gate. How do you make that enable signal. That signal will have a start. What signals do you ADD together to make the start of that enable gate. Then once you figure that out, what signals do you AND together to end it.

 

I've got a project I don't know how to go about. I have two signal generators (A1 and A2). Each will output a different frequency and each frequency is adjustable. One frequency (A2) will always have a longer pulse length than the other. I need the longer frequency to gate the shorter one but in a way that does not change the pulse length of any of the shorter pulses. I also need this to happen no matter how much I change the frequencies. I have attached a picture showing what I am trying to do. You can see that the OUT pulses all have the same pulse length even when the other pulses A1 and A2 might cut them short if I used logic gates.


Initially I thought an 4071 OR gate would work, but once I simulated it in multisim some of the leading pulses were cut short and some of the trailing pulses were cut short.


How can I get the result I am looking for?

You do not want to touch the length of a pulse. How to handle when the (fast pulse) /(n* slow pulse) is not a integer number.
Under condition (fast pulse)> =(n* slow pulse)
In other words what you want is not possible when previous equation is true.

 

Sorry

So are you saying to put A1 through one input of the AND gate and A2 through the other, then on a second AND gate the combination of A1 and A2 on one input and A1 on the other?

Give me a few minutes to get my twins down for a nap, maybe then I'll be able to think...

Please, get your children to bed. Then, tell us what you want to do. That is a lot more efficient than playing "Twenty Questions." Besides, you don't not get money for every question..

John

 

@electronice123
Once you figure out how to generate a start and stop pulse/logic then you would use these signals to set and reset a flip flop, like a 74LS74.

 

avoiding truncation of the last A1 pulse during the A2 period is easy. Not so much avoiding truncation of the first A1 pulse. @electronice123, is it acceptable to not enable the first A1 pulse until the entire pulse occurs within the A2 period? In other words, if A1 is already active when A2 goes high, is it OK to ignore it? (A1)

Yes it would be ok to ignore it, the period of all the short pulses is not important, just that they are all the same length.

 

In addition to the delayed enable at the end of A2 that Les is talking about, you'll also need to delay the start of the enable at the beginning of A2. Also, you'll need to detect the edge of the A1 pulse. Once the leading edge of the pulse is detected, you'll need to turn on enable, and leave it on until the last pulse goes inactive, after A2 is low. This isn't incredibly hard, Les should be able to walk you through it. If he isn't available, I'll give it a whirl.

 

@electronice123
Do you know what the "set" and "reset" pins do on a flip flop? (Sometimes they are also called "preset" and "clear".)

 

@electronice123
Do you know what the "set" and "reset" pins do on a flip flop? (Sometimes they are also called "preset" and "clear".)

Yeah, the set basically turns the flip flop on allowing a high signal to pass through Q right?
The reset turns it off producing a low or 0 through Q'.....When Q is high Q' is low right?

 

So here's a quick attempt to try to understand this...

I use A2 as the SET. When A2 goes high it SETS the flip flop?

What do I use as the clock signal-and how do I know which type of flip flop I need D,JK, etc?

So I would input A1 and A2 to the inputs of a NOR gate, when each one was low the NOR gate output is high, this would then reset the flip flop?

Am I getting closer?

 

Yeah, the set basically turns the flip flop on allowing a high signal to pass through Q right?
The reset turns it off producing a low or 0 through Q'.....When Q is high Q' is low right?

Close enough.

OK, I'll give you the start logic. On the input of a NAND gate, connect A2 on one input and connect NOT A1 on the other. Connect the NAND output to the "Preset" pin of a 74LS74 flip flop.

 

Close enough.

OK, I'll give you the start logic. On the input of a NAND gate, connect A2 on one input and connect NOT A1 on the other. Connect the NAND output to the "Preset" pin of a 74LS74 flip flop.

Ok, what is NOT A1-Is that A1 inverted or A1 through a NOT gate?

 

@electronice123
A1 inverted

 

The trick is to have the gating function always go high before the first short pulse and low after the last short pulse to avoid shaving the pulses or generating glitches.
I believe I have a solution for that using a D-FF and a couple gates, but I won't post it until the OP has made a further stab at the solution.

One question is:
Is it acceptable to have the first short pulse shorted by the propagation delay of the FF and a gate?

 

With all the wonderful solutions offered, you may want to step back and think about how they work or not work.

I would offer that if you cannot think of a way for you to do it, there is no way any thing electronic can do it.

 

Danny, maybe you haven't noticed but several of us are very clear as to the success of this circuit.