tried that with what I have available to no avail. I only have the circuit running on breadboard which is not ideal, surely i would not see results as bad as this when the load is applied though? Is layout this critical? I will try soldering to prototype board and reducing lead lenths etc

 

Layout is very critical for switchers. You want to have Cin as close to the IC as possible to minimize its loop size.

I just looked through the datasheet and there is a suggested layout-- which you probably already saw. This will be very helpful to use as a reference.

 

should Cin be low esr also?

 

Lower ESR is better for input caps since they do not dip as much. I'd use a combination of ceramic and tantalum. The ceramic to reduce ripple voltage and the tantalum as bulk capacitance to help when the load changes.

 

tried that with what I have available to no avail. I only have the circuit running on breadboard which is not ideal, surely i would not see results as bad as this when the load is applied though? Is layout this critical? I will try soldering to prototype board and reducing lead lenths etc

Layout is critical. As you draw more current from the supply your results will
get worse if your layout is not done properly.

Is your circuit on Vector board or a solderless breadboard? Don't waste your time with a solderless breadboard. If you want to build a prototype board use the Vector 169P84WEC1 and use a dremel tool to remove excess copper.

You should be able to get reasonably layout with the 169P84WEC1 board. It will take
you a little time to layout and build.

(* jcl *)

 

Please your probrem a high current look this!!!

 

Ive shifted the circuit onto some prototyping board, with no change in results really. Its a tough one to get done nicely on a breadboard though, im thinking i may just accept the design and build it into my pcb. at least then i can use decent SM components and get the capcitors right. The ripple doesnt actually seem to affect the rest of my circuit too much, but who knows how long components will last like that! Is inductor choice critical also? At the moment im using this one http://www.farnell.com/datasheets/94423.pdf currently trying 33uH, but was using 10uh

 

an update, i have the design now on a pcb, with slightly improved results. I am seeing around 200mV ripple. However i cant seem to get the last little bit of performance out of the circuit, i have tried changing capacitor values, larger inductors, yet nothing seems to improve this ripple. I am using a 100uF low esr surface mount cap on the output, 10uf low esr on the input. inductor is currently 10uH. I need to get rid of this ripple completely, because our application is very sensitive.

 

What frequency is the ripple? Can you filter it out or put a post-regulator LDO after it? Try adding a small cap on the output side in parallel. Another thing to look at is the compensation network. You can put something like a 470R resistor in series with Vc to help stability.

What is the load current you are testing at?

 

Buck Regulator App note EE-228

The application note linked to above has a pretty good presentation of the various contributions to ripple. Maybe it will provide you with some insight into your ripple problem.

hgmjr

 

ok knowing a bit more about oscilloscopes might help im looking at the 5V output, with the scope setting on 2V/div i see 200mVp-p ripple, with a 1V division its only 80mVp-p which is acceptable.. I think if i use the scope properly the results arent so bad! Whats the explanation for this, im sure its simple but i cant quite see it not knowing too much about scopes... its an agilent DSO3102.

 

The digital scope should not affect the signal amplitude just because you changed the channel gain from 2V/div to 1V/div.

Have you tried adjusting the timebase to expand the display so that you are looking at only a couple of cycles of the ripple waveform?

hgmjr