hello,

im a total newb, so please be a little bit patient with me;
im looking for a way to handle by means of a microcontroller a rather big amount of dram; most devices i found so far only do up to 2 or 4 gigs or ram and i definitely need more, im aiming for 16 gb; the memory itself will hold only data, its meant to be a buffer; the speed range, depending on the final interface, from 40-60 to over 200 mb/s (memory bandwidth); could anyone suggest how i can attain such an amount of memory on any 32bit microcontroller? or are there 64bit device on the market with a more or less normal price tag? if not a device, with an integrated dram controller, maybe an external controller attached to a 32 bit controller could do more memory? but would it perform attached via gpio or whatever? or is this a task for a fpga to simulate a wider adressable range?

thanks
m

 

I recommend that you build a virtual memory controller if you can stand the address translation delay. What device is going to generate such large addresses?

 

thanks for the quick reply;
i would have to wrap my mind around this idea first; by virtual memory controller you means thh alike to pae technology from intel? the large adresses are not a must, its for example a video source that will quickly generate a huge amount of data i need to make sure i wont slow down the saving of that stream, so i dont really look for large adresses, more for huge memory capacity with guaranteed bandwidth;

 

OK so what I mean by a virtual memory controller is one that takes a n-bit address space and maps it into a m-bit address space, where:

\(n > m\)

This allows you to implement a memory hierarchy with different access times between the different levels of the hierarchy. You could implement this hierarchy with a mix of multi-gigabyte DRAM and multi-terabyte disk drives.

 

now i think i get it, thanks so i think the simplest way out would be to extend the existing memory controllers pins by some pins controlled via gpio to get longer adresses, but i dont think there is any mechanism to synchronise my fiddling with gpio with the memory controllers output, which afaik is a must for fast dram; another option i think there is, is to construct, most probably by means of an fpga device (how complex is that? any other way to do it? use a ready controller on the market? how? and how do i know the external controller will serve 4gb+ when the cpu only addresses 32bits?), an entire dram controller that would either, if possible, work in place of the built in one or be a gpio (is there any fast enough alternative?) steered external device that doesnt map onto the cpu address space but allows operations on memory locations; i also already checked price tags for some fpga testing samples and it all seems quite expensive, maybe i was looking for overly sophisticated devices?
any thoughts on that?