Hi.....I had a question regarding building a logic circuit using only NAND gates. Basically I seem to be able to boil everything else down but once I get to translating other gates into NAND or NOR...my mind shuts down. Theres just this gap in my head where I can't figure out what to do really....Im familiar with demorgans law, and what not yet I cant seem to translate it as well as i want to.....

Ive attached a little sheet below.....now first I simplified the boolean expression to something a lil smaller (although the simplified form is only right in my mind...just started to learn this stuff) ...from there Im trying to use only NAND gates. This is where im stuck. I will note that this a lab exercise for me so I'd appreciate rather than a straight answer maybe a slight walkthrough? Whats the best way to approach something like this?

Thanks in advance.

 

It's helpful to use the following relationships:

 

Your expression is fine. The diagram is as well. I think some people try to apply DeMorgans, but I would stay away from this until you have to do SOP form for more complex things.

I find it easier to simply take the logic diagram that you get from your original expression and substitute the equivalent NAND gates. It does require remembering what they are, but it really is not that bad. Sometimes it looks ugly at first, but if you pay attention to the "bubbles", you will be able to simplify it.

Check out http://www.kpsec.freeuk.com/gates.htm - scroll to the bottom of the page for some examples and equivalent gates...

 

Srry bout the late reply....the internet cut out for the last day and a half and I didnt get a chance to reply. So I thought through it and hopefully i made a proper logic gate using only NAND gates but if Im correct in the lab i can only use 4 Nand gates and my boiled down version has 5......could someone take a look and comment on what I did erroneously. Also this boiled down version is my equivalent from the first post.

 

I don't know how it can be done with 4 2-input NAND gates. However, I know it can be done if you use a 3-input NAND gate.

Construct the expression F=AB'C' with two inverters and a 3-input AND gate and turn them to NAND gates. You get 4 NAND gates, three with 2-inputs and one with 3-inputs.

 

This is a bit late, but in the lab, when you need a 0, just input a 0 using a switch and don't bother about the gates. I did it all the time last year. You just have to keep track of it. This way your circuit only needs 2 NAND gates.

Good luck

 

Care to show a circuit diagram with the reduced gates justtrying?

 

It may help in your understanding if you remember that a NAND gate performs the NOR gate function for negative logic (logic 1 being low and logic 0 being high). Thus if either one or both inputs are low (logic 1), the output is high (logic 0).

 

Care to show a circuit diagram with the reduced gates justtrying?

Sure. I like your suggestion but it doesn't work if circuit has to be implemented using NAND gates only. It sound like the lab involving exploration of "universality" of NAND gates...

feel free to correct if I am wrong, I am by no means an expert...

 

What you say stands theoretically, but in real life, modular implementation rarely allows you to change the whole system just to save a couple of gates.
Usually the you take the signal as-is and have to bend it into submission.

 

Yes, I know what you mean. In the lab, the attempt to make students implement everything with one gate can misfire (as seen above) - last year I was running out of room on my breadboard with imposed limitations (in terms of gates that could be used) so shoving in inverters is a nuisance and for all practical purposes what I proposed worked. Of course you cannot do it in real life...

Bend it into submission... does it really work... I feel like digital controls our life, if anything you can bend analog into submission... (although right now I wish there was an op-amp complaint department