Right.Not sure if this deserves an entire thread of its own so I will ask here, CKP sets the clock idle state high or low and CKE sets the data transmission from clk idle->active or active->idle right?
In this case, CKP=0 so SCK is normally 0 (idle).
CKE = 1 which makes the 'transmission of data' when SCK goes active->idle' i.e. SDO changes on the falling edge of SCL. That means that the data is stable on the rising edge of SCL which is what the display wants.
In Fig 24-6 of the datasheet, the 3rd line of clock pulses is CKP=0, CKE=1. Draw a line down from each edge of SCL and you'll see that SDO is stable on SCL rising edge and changes at the falling edge with that setup.