then i suggest that you look up the device

Are you serious?

Since you are the one asking for free help, I suggest that you post anything necessary to convey the context and details of the problem to an experienced professional. Schematic, component datasheets, photos of the assembly; what someone "in the know" calls information.

ak

 

It would appear that something is wrong.
I would suggest that you breadboard the circuit and post a well focused photograph of your layout.
Also post a sharp image of the markings on the chip.

 

"Also post a sharp image of the markings on the chip."

Yea...that might be a little difficult, I can barely read the markings these days, let alone get a clear picture.

Anyway...

Does the data sheet actually say the outputs can be tied together? Because this is something I would never try with CMOS outputs.

My gut says there is a possibility of propagation delays on the inputs to the outputs causing some shoot through across outputs.

Since that chip offers higher output current, it may behave differently than some others in the 4000 family.

Even small resistance differentials on the BB may cause these problems. (even if the inputs are not driven, and connected to a rail)

 

Does the data sheet actually say the outputs can be tied together? Because this is something I would never try with CMOS outputs.

An acceptable practice for gates in the same package.

 

What if there were some stray capacitance on the BB delaying the inputs, or a spike affecting one or more of them?

I don't see a problem under ideal conditions, but on a BB....pffffttt.

 

Did TS say that he has tied outputs 1, 4, 8, and 11 together for higher current drive?
Hmm. Maybe this is the wrong chip for that.

Do as @ebp says. Test each output separately.

 

4000 series CMOS is fairly slow, so even on a breadboard there isn't much chance of causing timing skew worthy of worry when paralleling devices. You might run into some issue with a low slew rate input signal. With high speed devices, more care would be in order.

A greater concern is adequate power supply decoupling. There is always some shoot-through current with CMOS - both the N and P devices are partially enhanced during the switching transitions. If you have several outputs switching at the same time, the current spike can be quite high and cause a disturbance in the force.

An old (but not as old as 4000 series) ap note:
https://www.fairchildsemi.com/application-notes/AN/AN-77.pdf

 

An acceptable practice for gates in the same package.

Actually, not always. It is outright banned by some divisions/projects of the big MIL contractors, frowned on by many more, and I think it gets a mention in MIL-HDBK-417 or DO-254 or Bellcore or one of the other high-reliability specs. Spidey is correct, differential delays among the internal circuits can cause cross conduction current spikes that damage internal components over time. That doesn't keep me from doing it in my personal stuff, but only after I consider how it will affect that particular circuit.

ak

 

Actually, not always. It is outright banned by some divisions/projects of the big MIL contractors, frowned on by many more, and I think it gets a mention in MIL-HDBK-417 or DO-254 or Bellcore or one of the other high-reliability specs.

Do those contractors ever use any commercial microprocessors? It's very common to have multiple P and N MOSFETs in parallel to increase drive strength. As I recall, some of the microprocessor projects I worked on had inverter strengths from A to K and drive strength was increased by connecting more devices in parallel.

For some designs, the legging requirement (max gate width by process design rules) required legging on many standard cells. In later process generations, they removed the legging penalty (loss of effective width), so it didn't take more area to leg. Polysilicon (they don't actually use polysilicon now, but they still call it poly) is so hard to pattern at the sub 22nm nodes that it wouldn't surprise me if they only had 1 or 2 allowable gate widths. We got rid of all of the analog design rules around 90nm.

Within the same package, device parameters are going to be matched pretty well. You could never get away with paralleling devices in separate packages, but doing it within the same package is done in microprocessors all the time.

 

Can someone with more experience of using 4000 series ic's explain what is going on with a very simple circuit. Those in the know won't need a schematic as it is self explanatory. I have a CD4047B wired as a standard astable running at around 100Hz driving a CD4041ub.
The astable works fine with a supply of 4.5 to 15 Volts, but the output from the unloaded CD4041 collapses as the supply is increased above 7.5 volts although the spec sheet shows it should also be fine at 15 Volts.
Pins 3,6,10,13 are linked and used as inputs, 1,4,8 11, are the outputs, 7 is -ve, 14 is +ve. There is a 1mfd tantalum and 100nf ceramic capacitor decoupling the supply pin to each chip, a 100mfd electrolytic close to both i.c's across the supply input, and I have tried using two different lab power supplies.
Driving a CD4049 or CD4050 in a similar fashion works with no problems up to 15 Volts.
The circuit is to be used purely as a pulse generator to test logic circuit experiments, with 5 volts supply it will drive ttl ic's, but I want the option to drive Cmos as well.
I have tried two more CD4041's with the same result, they were supplied new from R.S supplies and not from any dubious source.
I'm sure there must be something simple I am overlooking, but I do not have a lot of experience with working with logic I.c's.

PROBLEM SOLVED.
My original post, then followed up with specific answers to helpful questions, which then led to some answers that pointed me in the right direction. (and some that rather than help, liked to quote out of context, or make assumptions as to my understanding of the difference between cmos and ttl without reference to the specific device)
Yes, whilst I am not expert with logic, I can read data sheets and follow established working practices well enough to understand the principles of operation. But, when an oddity such as I described occurs, my request was simple. "those in the know" meaning anyone with far greater experience working with the 4000 series, may have encountered similar problems and have a quick answer. If not, then, why bother to reply to the thread at all?
The answer I found, is subtlety hidden in data sheet, . Some so called "professionals" not spotting it either.
Nothing to do with the parallel connections, advice which I took from a book on cmos written by a design engineer from one of the largest manufacturers of logic ic's.

Thanks to those who had a positive approach to solving the problem, to the other "experts," take a look at the data, and see if you can identify the cause. because once you see it, it's obvious.
Anyway, I'm happy to end this thread here as I now have it working just as I wanted.

 

@recklessrog
AAC forum is a cooperative site where we help each other regardless of skill level and expertise, without snarky attitudes.
Please remember this next time you seek help here on ACC.

 

@recklessrog
AAC forum is a cooperative site where we help each other regardless of skill level and expertise, without snarky attitudes.
Please remember this next time you seek help here on ACC.

Take a look at the miss quote and and comments made to me then!

 

I don't see any miss quote.

If any member is requesting assistance in anything electrical and electronics on AAC forums then it is expected that that member should provide circuit schematics, links to applicable references and datasheets and all pertinent information. It is not acceptable that others should have to go and look things up by themselves.

When a solution has been discovered, it is simple courtesy to reveal and describe to the membership at large what was the solution.

 

I looked at the Intersil datasheet and can see nothing that accounts for the behavior. The only oddity I could see is related to the input threshold levels for the complement output which is unbuffered. Due to lack of buffering the transfer characteristic for the complement outputs is sloppy (much less "square"), the result of which is that the specs for Vin differ somewhat from 4000B series (LOW is lower and HIGH is higher) but this is still totally compatible with the output of a 4000 series device operating at the same supply voltage.

[edited]

 

using a 4049/4050 everything is fine so I may just use them instead

I prefer using CD4049/50. In addition to having drive characteristics similar to CD4041, there are more gates (assuming you don't need complementary outputs), and they have different input protection than other CD4xxx logic that allows them to do high to low voltage conversion.

 

I don't see any miss quote.

If any member is requesting assistance in anything electrical and electronics on AAC forums then it is expected that that member should provide circuit schematics, links to applicable references and datasheets and all pertinent information. It is not acceptable that others should have to go and look things up by themselves.

When a solution has been discovered, it is simple courtesy to reveal and describe to the membership at large what was the solution.

I'm amazed that experts would need a circuit of a buffer. If they don't know what it is, then don't reply, but when specific application description is provided, and they still don't understand, even more reason not to reply. Actually I did upload the data file, AND to save any more controversy, asked that the thread to be closed, but no, the sniping just continued.

I have been a contributing member long enough to know how it works, so when I can help and have a POSITIVE input, I reply. Otherwise, I stay silent.

 

I looked at the Intersil datasheet and can see nothing that accounts for the behavior. The only oddity I could see is related to the input threshold levels for the complement output which is unbuffered. Due to lack of buffering the transfer characteristic for the complement outputs is sloppy (much less "square"), the result of which is that the specs for Vin differ somewhat from 4000B series (LOW is lower and HIGH is higher) but this is still totally compatible with the output of a 4000 series device operating at the same supply voltage.

[edited]

Yes, that is the reason, and also the input protection seems to add to the problem, as d1324 noted above.

 

Well as it seems that some are confused by what a Quad ttl buffer is, (a basic logic ic building block) let us close the thread and once I've worked out what is happening myself, I will keep it a secret and happily continue with the project.
I don't need any help with the pin outs, they are in the data sheet. It is the strange behaviour of this particular IC that I was questioning. If you just want to make comments without taking the time to look at my question, maybe even check it's data etc, then unhelpful comments are not welcome!
To those who actually offered constructive advice, I thank you.

Hey Reckless, don't let the turkeys get you down. I've had similar problems with posting junkies with a bee in their bonnets; just ignore them.
You are quite correct, the circuit does not need to be published. I think I can manage to hold the thing in my head, being 4 buffers in parallel and an astable is not exactly a huge stretch of the brain.

First up, I will say: beware all UB suffix 4000 series parts. The UB usually stands for 'unbuffered' and these parts are typically very very static sensitive. Having said that, the data sheet does not state what static immunity standards it might meet and neither the TI nor ST data sheets mention latchup at all. I suspect the problem you are experiencing could be a form of latchup in the output drivers.

Unlike the usual buffer or inverter gate the 4041 is a line driver so the output stage has a more substantial current capability so if two outputs are connected together but don't change state at exactly the same time then they will fight. Couple that with the shoot-through conduction during the state changes which will help the first gate to change state win the fight. The fighting during transitions may possibly explain the distortion you see before the output dies away completely. When it dies totally above 7.5V (I think you said) then that could be a latchup problem which would be aggravated by the heat generated during the fights in transitions.

Before I go any further though and you may have already mentioned this and I missed it, does the 4041 get warm or hot when it is this non functional state with Vdd > 7.5V?

 

Hey Reckless, don't let the turkeys get you down. I've had similar problems with posting junkies with a bee in their bonnets; just ignore them.
You are quite correct, the circuit does not need to be published. I think I can manage to hold the thing in my head, being 4 buffers in parallel and an astable is not exactly a huge stretch of the brain.

First up, I will say: beware all UB suffix 4000 series parts. The UB usually stands for 'unbuffered' and these parts are typically very very static sensitive. Having said that, the data sheet does not state what static immunity standards it might meet and neither the TI nor ST data sheets mention latchup at all. I suspect the problem you are experiencing could be a form of latchup in the output drivers.

Unlike the usual buffer or inverter gate the 4041 is a line driver so the output stage has a more substantial current capability so if two outputs are connected together but don't change state at exactly the same time then they will fight. Couple that with the shoot-through conduction during the state changes which will help the first gate to change state win the fight. The fighting during transitions may possibly explain the distortion you see before the output dies away completely. When it dies totally above 7.5V (I think you said) then that could be a latchup problem which would be aggravated by the heat generated during the fights in transitions.

Before I go any further though and you may have already mentioned this and I missed it, does the 4041 get warm or hot when it is this non functional state with Vdd > 7.5V?

Thank you for the very positive response. Yes I discovered that as the fault condition arose, the current being drawn jumped from 13 ma to 56 m.a so I lowered the current limit from the psu to prevent overheating and destroying the chip. It was indeed latching up, and also being un-buffered as you pointed out, caused the effect. Your description would certainly explain the behaviour.

 

We are not confused but you seem to be
TTL is bipolar logic, not CMOS, and can't operate above 6V.

The strange behavior is likely due to a wrong connection on your circuit but, since you refuse to post a circuit schematic, we can't really help you further.

It is a buffer, implemented in CMOS and may be used to convert CMOS levels to TTL levels which can then also drive actual TTL inputs (as opposed to CMOS inputs with TTL thresholds). So that clears up a very silly argument which has nothing to do with the original post. I also don't think Reckless need publish a schematic as it really is a simple circuit and more to the point a generic question for a single part. If you really don't agree about the need to publish a schematic it is no reason to carry on about it. Obviously not everybody is going to consider your words of wisdom to be pure gold but that should not offend you as it obviously has Crutschow et al. That's just the way the cookie crumbles some times.

 

Thank you for the very positive response. Yes I discovered that as the fault condition arose, the current being drawn jumped from 13 ma to 56 m.a so I lowered the current limit from the psu to prevent overheating and destroying the chip. It was indeed latching up, and also being un-buffered as you pointed out, caused the effect. Your description would certainly explain the behaviour.

Bingo! The 56mA is smaller than I expected but then I didn't put too much thought into how much current it might be either. Like you, I am much happier with a plausible, if not definitive explanation for these things so the mistake I can avoid next time. We live and learn. Good luck with the rest of your project.