Hi:

I am trying to figure out why my DC Sim results differ from my hand calculations
for some voltages and currents but not all. I have attached the sim file, the schematic,
the DC sim results and an excel sheet comparing the two sets of results. I found that
this didn't happen with other circuits that I have studied.

Thanks

 

I disagree with the voltage on the base of Q1. Didn't go any further.

Is this homework?

 

Considereing that the sim is using a much more complicated model than you are with your hand calculations, the results look pretty consistant to me.

 

I disagree with the voltage on the base of Q1. Didn't go any further.

Why?
The calculated and simulated values are quite close.

I also think the calculated and simulated values for the other parameters are in reasonable agreement.

 

What value for transistor beta did you use in your calculation? If it differs from that in the Spice model you should expect different results.

 

What value for transistor beta did you use in your calculation? If it differs from that in the Spice model you should expect different results.

Actually I used Beta = 125 but the "P" version of the transistor also has a Beta =125.

Why?
The calculated and simulated values are quite close.

I also think the calculated and simulated values for the other parameters are in reasonable agreement.

Thanks. That is good news, I wasn't sure just how much of a variance is acceptable. I am interested to see
the results when I actually breadboard the circuit.

Considereing that the sim is using a much more complicated model than you are with your hand calculations, the results look pretty consistant to me.

Thanks. That is good news.

 

You and the simulation software are just guessing that some of the transistors you buy will have a "typical" beta of 125.
Why not calculate using the entire range of beta from about 80 to about 300? The datasheet shows a typical beta of 225.

 

Why?
The calculated and simulated values are quite close.

I also think the calculated and simulated values for the other parameters are in reasonable agreement.

Does stage 2 have a loading effect on stage 1 since it provides the dc bias for stage 2? If so, would this
account for some of the variance between the hand calculations and the sim? How would you determine
the magnitude of the loading effect?

 

Your output transistor has its emitter resistor bypassed with a capacitor so its emitter resistor does not produce any negative feedback resulting in very high distortion at high output levels. The input transistor operates at much lower output levels so it should have its emitter resistor bypassed, not the output transistor. Then the distortion will be much less.

I played with the simulation with the first transistor having its emitter resistor bypassed instead of the first transistor but I could not get the transistors biased correctly using normal resistor values and tolerences since the DC gain is too high with missing DC negative feedback

Here is the severe distortion at the output of your design with the input level only a little higher than conversation level into a microphone:

 

I also think that your hand calculations are ok nothing to worry about.

And yes, you can include the second stage loading effect.

We have this situation:

IRc1 = Ic1 + Ib2

Ib2 = (Vcc - Rc1*(Ic1 + Ib2) - Vbe2 )/( (β+1)*Re2 ) --> Solving this we have:

Ib2 = ((Vcc - Vbe1) - Rc1*Ic1)/(Rc1 + (β+1)*Re2 )

Ic1 ≈ 320μA so we have

Ib2 = ((12V - 0.6V) - 22kΩ*0.320mA)/(22kΩ + 126*10kΩ) = 3.4μA

As you can see omitting Ib2 in calculations do not bring much of an error many due to large Re2 value and the beta >100.
Because the Re2 is seen at the T1 collector as a 10kΩ*126 = 1.26MΩ resistor.

 

I also think that your hand calculations are ok nothing to worry about.

And yes, you can include the second stage loading effect.

We have this situation:

IRc1 = Ic1 + Ib2

Ib2 = (Vcc - Rc1*(Ic1 + Ib2) - Vbe2 )/( (β+1)*Re2 ) --> Solving this we have:

Ib2 = ((Vcc - Vbe1) - Rc1*Ic1)/(Rc1 + (β+1)*Re2 )

Ic1 ≈ 320μA so we have

Ib2 = ((12V - 0.6V) - 22kΩ*0.320mA)/(22kΩ + 126*10kΩ) = 3.4μA

As you can see omitting Ib2 in calculations do not bring much of an error many due to large Re2 value and the beta >100.
Because the Re2 is seen at the T1 collector as a 10kΩ*126 = 1.26MΩ resistor.

Hi Jony.

I am trying to figure out how one would go about designing this circuit. Would you select VCE (based on the desired peak
output voltage) and IC for stage 2 and then work backwards to stage 1?

aac

 

I am trying to figure out how one would go about designing this circuit.

As I said previously, this circuit is missing AC and DC negative feedback. It also has the emitter capacitor on the wrong transistor.
Since the transistor beta is a range of numbers, the circuit should be designed to work with any passing 2N3904 transistor with a beta from 80 to 300.

 

Hi Jony.

I am trying to figure out how one would go about designing this circuit. Would you select VCE (based on the desired peak
output voltage) and IC for stage 2 and then work backwards to stage 1?

aac

Yes. I would go backwards, from the output to the input. And add some negative feedback.

 

Yes. I would go backwards, from the output to the input. And add some negative feedback.

thanks