Hello, after researching i found out that its actually better making push-pull stages with MOSFETs

In this configuration i put both of the drain in common, and i changed the input ( square wave ) to 0-12.

Do u guys think this design Is fine? i will be able to drive the gate of the MOSFET at 1A? ( I didnt put any series resistor should i put one (?) )

In case how i should change my circuit?

The components i chose are : IRLZ44N and IRF9530 for the totem pair
While the MOSFET that will be driven is: IXTH360N055T2

 

What did the simulation show?

 

Do u guys think this design Is fine?

it is fine as long everything is within specs. that is how typical logic circuits form inverters.
12V is fine for most but it may kill some mosfets

 

Okay, I'll do it myself.

4,577,400,000,000 Amps flowing through the two MOSFETS.

 

No - that won't work.
1. You have M1 and M2 back to front. If you want a non-inverting stage, then the drains go to the supply and the sources go to the output. As you have drawn it, you have the two body diodes in series shorting out the power supply.
If you want an inverting stage, then both devices have their sources connected to the supplies, and the output is on the drains, but the P-channel goes to the positive supply and the N-channel to the negative.

2. If wired as a non-inverting stage, it is a source follower, so the output voltage will only vary from about 3V to 9V. IRLZ44 is a logic-level MOSFET, it will be on with 2V on the gate. It will never turn off.

 

What did the simulation show?

Sorry, i think i did a mistake, mosfet P and mosfet N gotta be switched in the schematic

 

No - that won't work.
1. You have M1 and M2 back to front. If you want a non-inverting stage, then the drains go to the supply and the sources go to the output. As you have drawn it, you have the two body diodes in series shorting out the power supply.
If you want an inverting stage, then both devices have their sources connected to the supplies, and the output is on the drains, but the P-channel goes to the positive supply and the N-channel to the negative.

2. If wired as a non-inverting stage, it is a source follower, so the output voltage will only vary from about 3V to 9V. IRLZ44 is a logic-level MOSFET, it will be on with 2V on the gate. It will never turn off.

Yeah i gotta switch the MOSFET P with the N

 

4,577,400,000,000 Amps ...

LOL... that IS some current...

 

LOL... that IS some current...

View attachment 357561

Your PMOS body diode is forward biassed.

 

LOL... that IS some current...

View attachment 357561

Ahaha, yeah how i connected the FET makes the vdd goes directly in shortcircuit to gnd, my bad, i kinda suck but whatever

 

Your PMOS body diode is forward biassed.

you are correct of course... i better get some rest...

 

 

View attachment 357564

Ok i have swapped the N and P as u did, and now driving the FETs at 12V, but why i dont see any current at the gate of the N mos? I have added a little resistor of 1Ohm and measured current, but i see it 0A

 

why i dont see any current at the gate of the N mos?

What amount of current were you expecting at the gate?

And it's best to use real models for the MOSFETs as the default generic can have odd characteristics.

 

Okay, I'll do it myself.

4,577,400,000,000 Amps flowing through the two MOSFETS.

View attachment 357541

That’s real lesson in not using the SPICE generic devices. How could any real device have an on-resistance or body-diode series resistance that low?

 

What amount of current were you expecting at the gate?

And it's best to use real models for the MOSFETs as the default generic can have odd characteristics.

What amount of current were you expecting at the gate?

And it's best to use real models for the MOSFETs as the default generic can have odd characteristics.

Well i wanted to have atleast 1A, in order to approximate It i used ohm law, so I= Vout/Rout+R series, so i= 12V/1.2Ohm = 9A or around that value.

The average current i calculated It in a different way:
Iavg=QG•fsw , where QG Is 330nC and fsw= 10KHz

Iavg=330•(10-⁹)•10•10³=3.3mA


I try putting real models? But where can i find like a book or so explaining how do find expected current

 

So how you you measuring the gate current?
That current occurs as a very short spike to charge the gate capacitance.

 

So how you you measuring the gate current?
That current occurs as a very short spike to charge the gate capacitance.

I tried measuring the current on LTSpice, but now im trying to import real models and see if the expected current Is as i calculated or not, lets see what i find out

 

get impedance is high, why do you expect gate current to be 1A?

 

The gate may indeed draw 1A, but only for nanoseconds. Change the scale on your simulation and you might see it.