I've gone through the DS1307 datasheet multiple times, trying to determine which clock edge it uses for data reception from the master and data transmission to the master. However, I couldn't find this specific information in the datasheet. The only relevant diagram I found was Figure 8 on page 11, but it didn't provide a clear information. As many mentioned before on a forum, data can often be transferred or received on either the rising edge or falling edge of the clock, and I believe the configuration of the clock edge is determined by the slave device. Therefore, we should be able to configure the master's clock accordingly

 

The way I read it, it does not matter. The data must be stable for the entire high period of the clock, so the results will be the same whether the data is latched on the rising edge or the trailing edge, or anywhere in between.

 

The way I read it, it does not matter. The data must be stable for the entire high period of the clock, so the results will be the same whether the data is latched on the rising edge or the trailing edge, or anywhere in between.

Do you agree that in the I2C protocol, data is typically transferred or received at the clock edge, not for the duration of the clock high or low?

During the low period of the clock, data may change, and during the high period of the clock, data should remain stable.

If I ask to you on which clock edge data would transfer and receive in I2C, how do you determined on either the rising or falling edge of the clock what would your reply on this matter?

I'm interested in understanding the selection process of clock edge for i2C based application development. As an application developer, what factors should we consider when choosing a clock edge , and why perticular should select? I'd appreciate your help on this matter

 

I have no experience with I2C, so I cannot answer your question.

Can you tell me why you are concerned with which edge latched the data on the DS1307 you are talking about? Assuming you do not violate the requirement that the data is unchanged during the entire high period, how could you even tell? How would it change what you did to interface to it?

 

Hi Mtech1
Do you have a copy of this PDF?' s
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Apparently 2-wire is an attempt to avoid the trademark of I2C.


For triggering, I found this.

I2C is a Level Triggering. A device that sends data onto the bus is defined as transmitter, and a device receiving data is defined as receiver. The bus has to be controlled by a master device which generates the Start and Stop conditions, while the Some devices like LCD, EEPROM, RTC are works as slave.

 

The information is on Figure 8 of the datasheet. The data setup and hold times are shown and specified on page 10.

 

Can you tell me why you are concerned with which edge latched the data on the DS1307 you are talking about?

I came across link on internet now forgotten link suggesting that the master transfers data on the falling edge, and the slave receives data on the rising edge. This prompted me to wonder under what conditions the master could transfer data on the rising edge and when the slave could receive data on the falling edge

 

It's I2C, so at a guess, it works like it says in the I2C spec.
https://www.nxp.com/docs/en/user-guide/UM10204.pdf

 

I came across link on internet now forgotten link suggesting that the master transfers data on the falling edge, and the slave receives data on the rising edge. This prompted me to wonder under what conditions the master could transfer data on the rising edge and when the slave could receive data on the falling edge

That sounds much more like a description of SPI than it does of I2C

 

Do you mean that we don't specify clock edges in I2C, as we do in the SPI protocol? In I2C, the sender should set the logic level (high or low) on the SDA line while the clock signal is low, and the receiver should read the status of SDA while the clock signal is high.

 

Do you mean that we don't specify clock edges in I2C, as we do in the SPI protocol? In I2C, the sender should set the logic level (high or low) on the SDA line while the clock signal is low, and the receiver should read the status of SDA while the clock signal is high.

No. It is specified in the standard. There are no options to change anything.

 

I2C is very different from SPI.

I recently wrote a blog on I2C example.

https://forum.allaboutcircuits.com/ubs/msp430-i2c-lcd1602-interface.1822/

 

No. It is specified in the standard. There are no options to change anything.

Thank you for clarifying. I now understand that in the I2C protocol, we cannot change the timing. Specifically, the sender sets the logic level (high or low) on the SDA line while the clock signal is low, and the receiver reads the status of SDA while the clock signal is high.

 

Thank you for clarifying. I now understand that in the I2C protocol, we cannot change the timing. Specifically, the sender sets the logic level (high or low) on the SDA line while the clock signal is low, and the receiver reads the status of SDA while the clock signal is high.

Yes, that is called level triggering as opposed to edge triggering.