Hi,

I am running Design Rules Check in KiCad/PBCNEW and I am prompted this error:
Q1-2 are transistors.



What should I do to solve this matter?

 

Change your DRC settings to the minimum your board house will accept.

 

The spacing between pins on the transistors is almost nothing.

You could edit the foot print and spread the leads a little. Or you could make the copper around the holes smaller.

 

The spacing between pins on the transistors is almost nothing.
View attachment 212458
You could edit the foot print and spread the leads a little. Or you could make the copper around the holes smaller.

And when the TS progresses to TQFP devices, how would you deal with them? DRC default settings in many programs are so 1990.

Edit: TS may need to adjust the "annular ring" around THP pads. In Eagle, that is called "restring." It is a percentage of the hole diameter.

 

Did you modify the TO-92_inline package? The one from the library works fine for me with default DRM settings.
If you go with Ron's suggestion you can use the TO-92_inline_wide which has double the pitch. I always use the wide package because it makes DIY etching easier.

 

Did you modify the TO-92_inline package? The one from the library works fine for me with default DRM settings.
If you go with Ron's suggestion you can use the TO-92_inline_wide which has double the pitch. I always use the wide package because it makes DIY etching easier.

I did not modify. Actually the NETLIST had already chosen the footprint for Q1-2 by itself.

I have assigned the _wide model instead as you said, and I saved it, generated net-list, updated the pcb from netlist with confirmation of the changes and the DRC still prompt with the same error. What should I do?

 

 

oh now it works!

It wasnt enough to choose Netlist -> Update

I had to choose the "Update PCB from schematic" icon.

 

So whats the next step for me? to route?

I dont understand why it doesnt route itself. It knows where the wires are connected.

 

The board program should always know what's connected to what if it is consistent with the schematic. What is doesn't know is the paths for the connecting traces.

Many cad programs have "autorouting." KiCAD does too, I think. You can try it, but many of us (myself included) prefer to manually route. Sometimes, I will use autoroute to get an idea or perhaps change device locations/rotations, but then I manually route.

If your design includes multiple, almost identical subunits, it may help to route one until you are happy with placements and connections, then follow that template for the others. Some devices require specific routings. In that case, it may help to route those devices first, then try autorouting for the remainder.

 

Thanks

I think my ratsnest looks horrible, doesnt it?. How do I know how to place the footprints the right place?

 

There is no one "right place." You know your schematic, do something logical. For example, if you have three chips that have many connections between them, don't put them at the apexes of an equilateral triangle. Don't put a decoupling capacitor across the board from what it is decoupling.

Schematics usually have a certain flow -- left to right and top to bottom. With a board, you need to consider where power connections, user buttons, and so forth need to be placed.

Here's a rough ratsnest (left image):

On the right is what was submitted to Oshpark. NB: The ratsnest is not identical. As I moved through the design, I needed to add other constraints, like where the switches were located and outline. I also changed the MCU.

The first ratsnest you get can be overwhelming. Just work through it logically in small parts. Don't try to attack it all at once or perfectly. Develop a way to track your attempts, so you can go backward.

Let me add, that as a crutch, I usually route power and ground last. In fact, I hide the ratsnest/airwires for power and ground until I have a much better idea for the other connections.

 

Thank you.

So i've started to do as you advised me to. Moving the footprints around to. When moving a footprint the ratsnest connections/threads/wires is moving around to other connections. Is that normal? is it suggetions for me or why is it doing it?

 

oh its called airwires. They are moving around when I move the footprints.

 

oh its called airwires. They are moving around when I move the footprints.

Exactly. Now see if you can untangle all of them.

 

I actually think I did a good job untangeling them autorouter were able to route them on two layers.

 

I actually think I did a good job untangeling them autorouter were able to route them on two layers.

That is how I run a few tests cases before manually routing. Autorouting will be a lot quicker at finding issues that can be solved by rotating or moving a component.