Solution to "Pad too close to Pad"

jpanhalt

Joined Jan 18, 2008
11,088
The spacing between pins on the transistors is almost nothing.
View attachment 212458
You could edit the foot print and spread the leads a little. Or you could make the copper around the holes smaller.
And when the TS progresses to TQFP devices, how would you deal with them? DRC default settings in many programs are so 1990.

Edit: TS may need to adjust the "annular ring" around THP pads. In Eagle, that is called "restring." It is a percentage of the hole diameter.
 
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hrs

Joined Jun 13, 2014
362
Did you modify the TO-92_inline package? The one from the library works fine for me with default DRM settings.
If you go with Ron's suggestion you can use the TO-92_inline_wide which has double the pitch. I always use the wide package because it makes DIY etching easier.
 

Thread Starter

christiannielsen

Joined Jun 30, 2019
337
Did you modify the TO-92_inline package? The one from the library works fine for me with default DRM settings.
If you go with Ron's suggestion you can use the TO-92_inline_wide which has double the pitch. I always use the wide package because it makes DIY etching easier.
I did not modify. Actually the NETLIST had already chosen the footprint for Q1-2 by itself.

I have assigned the _wide model instead as you said, and I saved it, generated net-list, updated the pcb from netlist with confirmation of the changes and the DRC still prompt with the same error. What should I do?
 

jpanhalt

Joined Jan 18, 2008
11,088
The board program should always know what's connected to what if it is consistent with the schematic. What is doesn't know is the paths for the connecting traces.

Many cad programs have "autorouting." KiCAD does too, I think. You can try it, but many of us (myself included) prefer to manually route. Sometimes, I will use autoroute to get an idea or perhaps change device locations/rotations, but then I manually route.

If your design includes multiple, almost identical subunits, it may help to route one until you are happy with placements and connections, then follow that template for the others. Some devices require specific routings. In that case, it may help to route those devices first, then try autorouting for the remainder.
 

jpanhalt

Joined Jan 18, 2008
11,088
There is no one "right place." You know your schematic, do something logical. For example, if you have three chips that have many connections between them, don't put them at the apexes of an equilateral triangle. Don't put a decoupling capacitor across the board from what it is decoupling.

Schematics usually have a certain flow -- left to right and top to bottom. With a board, you need to consider where power connections, user buttons, and so forth need to be placed.

Here's a rough ratsnest (left image):
1595163711800.png1595163785854.png
On the right is what was submitted to Oshpark. NB: The ratsnest is not identical. As I moved through the design, I needed to add other constraints, like where the switches were located and outline. I also changed the MCU.

The first ratsnest you get can be overwhelming. Just work through it logically in small parts. Don't try to attack it all at once or perfectly. Develop a way to track your attempts, so you can go backward.

Let me add, that as a crutch, I usually route power and ground last. In fact, I hide the ratsnest/airwires for power and ground until I have a much better idea for the other connections.
 

Thread Starter

christiannielsen

Joined Jun 30, 2019
337
Thank you.

So i've started to do as you advised me to. Moving the footprints around to. When moving a footprint the ratsnest connections/threads/wires is moving around to other connections. Is that normal? is it suggetions for me or why is it doing it?
 
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