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Hello,
I want to integrate a 1Gbps ethernet switch into a design that I am making. I need to have 6 ports and that this switch performs the functions of layers 1 and 2 of the OSI model. For this I understand that I need 6 interfaces with a MAC block and with a PHY block and that I can dispense with the SGMII / RGMII / MII / RMII standards if they already have the PHY block implemented.
When selecting the chip there are 4 possible candidates that meet my requirements:
https://www.microchip.com/wwwproducts/en/KSZ9477
https://www.microchip.com/wwwproducts/en/KSZ9567
https://www.microchip.com/wwwproducts/en/KSZ9896
https://www.microchip.com/wwwproducts/en/KSZ9897
I need to make the design as simple as possible, so I think the most suitable will be the KSZ9896, since it incorporates the MAC and PHY interfaces in 5 ports (I will need to add one more PHY chip to achieve the 6 required ports). I understand that the 4 chips are a SoC that performs the functions of Ethernet switch, so it is not clear to me what sense it is to use an adittional CPU as is required in all, except in KSZ9896. I want to use KSZ9896 because no CPU is needed.
On the other hand in the case of chips that requires CPU I have been able to verify that both are connected to each other through the pins SGMII / RGMII / MII / RMII, which if I have understood correctly used to communicate the MAC interface with the PHY interface, so this is something that baffles me.
My idea is to use the KSZ9896 and do the design without using CPU. Am I right or is there something wrong with my reasoning?
If anyone can make it clear to me, I'll be very grateful.
Thank you
I want to integrate a 1Gbps ethernet switch into a design that I am making. I need to have 6 ports and that this switch performs the functions of layers 1 and 2 of the OSI model. For this I understand that I need 6 interfaces with a MAC block and with a PHY block and that I can dispense with the SGMII / RGMII / MII / RMII standards if they already have the PHY block implemented.
When selecting the chip there are 4 possible candidates that meet my requirements:
https://www.microchip.com/wwwproducts/en/KSZ9477
https://www.microchip.com/wwwproducts/en/KSZ9567
https://www.microchip.com/wwwproducts/en/KSZ9896
https://www.microchip.com/wwwproducts/en/KSZ9897
I need to make the design as simple as possible, so I think the most suitable will be the KSZ9896, since it incorporates the MAC and PHY interfaces in 5 ports (I will need to add one more PHY chip to achieve the 6 required ports). I understand that the 4 chips are a SoC that performs the functions of Ethernet switch, so it is not clear to me what sense it is to use an adittional CPU as is required in all, except in KSZ9896. I want to use KSZ9896 because no CPU is needed.
On the other hand in the case of chips that requires CPU I have been able to verify that both are connected to each other through the pins SGMII / RGMII / MII / RMII, which if I have understood correctly used to communicate the MAC interface with the PHY interface, so this is something that baffles me.
My idea is to use the KSZ9896 and do the design without using CPU. Am I right or is there something wrong with my reasoning?
If anyone can make it clear to me, I'll be very grateful.
Thank you
