Hello,

Can someone explain how the external cap and resistor affect the pulse output of this one-shot? I can't seem to wrap my head around it, especially because the datasheet says the cext pin is positive. Is this configuration correct? According to the datasheet, this should result in a roughly 5mS pulse. Pspice does not model these pins and relies on a parameter to define pulse width.



https://www.ti.com/lit/ds/symlink/s...=https%3A%2F%2Fwww.ti.com%2Fproduct%2FSN54121

 

Based on the external connections, the device acts as a monostable made from two NOR gates. Here is the basic circuit:



When the input goes high, the U1 output goes low. Ct pulls V1 low, which drives the output high. Positive feedback to U1 holds the U1 output low even if the input pulse returns low.

When both ends of Ct go low, Ct begins charging through Rt. This goes on until V1 crosses U2's input stage transition level. Not that for TTL gates this is not 63% of Vcc, so the monostable period is not simple equal to R x C; it is less because the transition level is lower. This is the reason for the K conversion factor in the datasheet equation. When V1 crosses the transition level, the U2 output goes low, terminating the output pulse. This low is fed back to U1, and enables the gate for another input pulse.

Once the output period is over, U1's output goes high and Ct discharges through Rt. For the next timing event to be the full length, Ct must be completely discharged. This can be hastened by placing a diode across Rt to partially "short it out" when V1 is greater than Vcc.

ak

 

Based on the external connections, the device acts as a monostable made from two NOR gates. Here is the basic circuit:

View attachment 255348
When the input goes high, the U1 output goes low. Ct pulls V1 low, which drives the output high. Positive feedback to U1 holds the U1 output low even if the input pulse returns low.

When both ends of Ct go low, Ct begins charging through Rt. This goes on until V1 crosses U2's input stage transition level. Not that for TTL gates this is not 63% of Vcc, so the monostable period is not simple equal to R x C; it is less because the transition level is lower. This is the reason for the K conversion factor in the datasheet equation. When V1 crosses the transition level, the U2 output goes low, terminating the output pulse. This low is fed back to U1, and enables the gate for another input pulse.

Once the output period is over, U1's output goes high and Ct discharges through Rt. For the next timing event to be the full length, Ct must be completely discharged. This can be hastened by placing a diode across Rt to partially "short it out" when V1 is greater than Vcc.

ak

Thanks for the feedback, for some reason your attachment link does not work.

 

Re-loaded the image. Try again.