I'm designing a 7-port USB hub powered by +12V instead of the usual +5V, and am working on the voltage regulator. After considering the safe option of a buck switcher down to 7V followed by an NPN linear output, I decided to use just the Buck switcher driven by a microcontroller rather than one of the popular chips, since this allows me to cope with both continuous and discontinuous modes by varying both duty cycle and clock frequency.


http://52midnight.com/tmp/Fig-1.gif

However, I'll need a good output filter, and I'm a novice at such design. What has always puzzled me are the criteria used to establish design parameters. The values of L1 and C1 emerge from the SMPS calculations, but I don't know where to start with L2 and C2.


http://52midnight.com/tmp/Fig-2.gif

As the equivalent circuit of Fig 2 shows, there are effectively two parallel resonant circuits in series. The first one rings at high frequency due to stray capacitance when the switch is off and current drops to zero, and I assume that the second would be sufficiently damped by the resistance of L2 after being "kicked" by the input waveform.

Can anyone suggest an analysis or alternative design approach that would result in optimum values for L2 and C2? Most grateful for any assistance here.


Mods Note:
Please upload your circuits to the forum.

 

C2 would be better made high value around 1000- 4700uF to give better smoothing, L2 would be determined by how much current you want to draw, if you have a software design try values from 10uH to 100uH.

 

Thanks for your reply. I trust you won't mind my saying that these figures, whilst both in the range I had contemplated, are simply ad hoc - sc. "guesstimates". This is the nub of my query: what criteria should be used to derive them?

My own thinking is that the value of L2 should probably be about ten times that of L1 in order to attenuate the switching transients it generates, and that C2 should be chosen so that the resonant frequency of L2/C2 is about ten times lower than the switching frequency. However, these are also just "guesstimates" based on elementary circuit analysis.

The matter is further complicated if the magnetic properties of L2's core are considered. I've seen some excellent theoretical presentations of all of this, and am aware of the paucity of my own understanding. SMPS design appears to be something of a "black art" in that, at the end of the day, experience probably counts for more than mere theory because of the multiplicity of conflicting requirements in establishing design criteria.

 

If you look at most Atx psus, they have dual inductors on the output side, with high value capacitors in the 5000uF range,

https://www.google.co.uk/url?sa=t&s...ggjMAA&usg=AFQjCNEJLor4_A0V0h9stgXV7VoeL-CWYA

 

Hey, that's a most useful link. Thanks! Many SMPS controller data sheets (e.g. MC34063) provide tables and ready-to-use equations for calculating component values in typical circuits, but only within specific constraints typical of most design requirements (and I even found an error in one equation in the foregoing).

The difficulty I face here is that the output current range is atypical: from a few tens of milliamps needed by the USB hub chip in idle mode up to the three amps design goal. With linear regs this is not a problem, even down to zero current, hence my initial (and still under review) idea of a switch-mode pre-reg operating in burst mode - on/off using a simple Schmitt comparator - with a linear output reg to keep things well-behaved.

The difficulty with SMPS at very low currents is that even a single switch cycle dumps more charge into the output circuit than you want, unless there's a second stage of filtering to level it off.

The ATX PSUs you referenced almost certainly have minimum current requirements below which they either switch off, or fail to regulate properly, and this is also typical of most SMPS designs.

I worry about using 12V and 5V SMPS plug-packs on the workbench to power experimental lash-ups for this very reason. The better-quality ones probably cope down to a few milliamps OK, but the cheaper ones may do very nasty things. I haven't got around to investigating this, but I'd say it's a caveat seldom recognized.

 

You also must consider the extra phase-shift from the added LC filter.
This can complicate stabilizing the control loop if you are sensing the voltage at the output of the second filter.

 

Good point. As in the schematic above, my initial decision was to sense at the first filter in order both to accommodate this and to give the micro "early warning" of changes. However, this might require a single RC filter in the feedback loop to prevent switching transients from confusing the control algorithm, and also introduces the phase problem you mention.

These things all look so nice and easy when you start out, and then the horrors come drifting in ...

 

hese things all look so nice and easy when you start out, and then the horrors come drifting in ...

Yes.
Notice the adage at the end of my post

 

Nice. I'll paste that over my design desk.

BTW, my thanks to the Moderator for linking in my schematics. I'm happy to upload them as requested if he'd provide a URL or whatever.

 

If you look at most Atx psus, they have dual inductors on the output side, with high value capacitors in the 5000uF range,

https://www.google.co.uk/url?sa=t&s...ggjMAA&usg=AFQjCNEJLor4_A0V0h9stgXV7VoeL-CWYA

Most I've looked in had 1000 or 2200uF - but those are the ones I had to re cap because they were confusing the hard drives.

Getting ESR as low as possible is just as important as huge reservoir capacity. At least 4700uF is normal on a linear, but a fast switching PSU changes the rules a bit.

 

> Getting ESR as low as possible is just as important as huge reservoir capacity.

This is one of the first and most important changes in thinking when moving from slapping together a diode bridge and a few large caps to designing SMPS. The old idea that "a capacitor is a capacitor" simply ain't true with el cheapo electros at SMPS frequencies - they're just blocks of bollocks.

Dodgydave's link brought this further consideration to the fore. I said above that "C2 should be chosen so that the resonant frequency of L2/C2 is about ten times lower than the switching frequency." Even as I wrote it I thought "Watch it!" If the switching frequency is progressively lowered, it will eventually come within resonant range of L2/C2, with adverse consequences.

A better idea might be to raise this Fr so that it's never excited. That is, instead of

L2 > L1 (about x10)
C2 > C1 (about x10)

... we choose

L2 > L1 (about x10)
C2 << C1 (about x100)

This means you get more higher frequency noise in the output at low currents, but these are typically powering standby circuits that are rated for wide supply variations and so aren't bothered by it.