I'm designing a 7-port USB hub powered by +12V instead of the usual +5V, and am working on the voltage regulator. After considering the safe option of a buck switcher down to 7V followed by an NPN linear output, I decided to use just the Buck switcher driven by a microcontroller rather than one of the popular chips, since this allows me to cope with both continuous and discontinuous modes by varying both duty cycle and clock frequency.
http://52midnight.com/tmp/Fig-1.gif
However, I'll need a good output filter, and I'm a novice at such design. What has always puzzled me are the criteria used to establish design parameters. The values of L1 and C1 emerge from the SMPS calculations, but I don't know where to start with L2 and C2.
http://52midnight.com/tmp/Fig-2.gif
As the equivalent circuit of Fig 2 shows, there are effectively two parallel resonant circuits in series. The first one rings at high frequency due to stray capacitance when the switch is off and current drops to zero, and I assume that the second would be sufficiently damped by the resistance of L2 after being "kicked" by the input waveform.
Can anyone suggest an analysis or alternative design approach that would result in optimum values for L2 and C2? Most grateful for any assistance here.
Mods Note:
Please upload your circuits to the forum.
http://52midnight.com/tmp/Fig-1.gif
However, I'll need a good output filter, and I'm a novice at such design. What has always puzzled me are the criteria used to establish design parameters. The values of L1 and C1 emerge from the SMPS calculations, but I don't know where to start with L2 and C2.
http://52midnight.com/tmp/Fig-2.gif
As the equivalent circuit of Fig 2 shows, there are effectively two parallel resonant circuits in series. The first one rings at high frequency due to stray capacitance when the switch is off and current drops to zero, and I assume that the second would be sufficiently damped by the resistance of L2 after being "kicked" by the input waveform.
Can anyone suggest an analysis or alternative design approach that would result in optimum values for L2 and C2? Most grateful for any assistance here.
Mods Note:
Please upload your circuits to the forum.