Single Phase PLL - Limits for Integral Path in Control Loop (PI Controller)

EDIT: Attached my hand written scribbles.

Evening gents,

I wrote a program that executes the following control diagram. The contents of the orange box titled, "Orthogonal system generation" is shown in the lower part of the Figure as indicated by the black arrow.



I did some analysis by hand to better understand how this control diagram works and have attached my scribbles, but I still have some unanswered questions.

1. I've read in several other papers that the output of the PI controller is \(\Delta \omega\). In my analysis I found that the input error signal to the PI controller was, \(\epsilon = V_{m} ( \phi - \hat{\phi} )\), and I cannot figure out how this becomes \(\Delta \omega\) at the output. Any ideas?
   
2. In the PI controller the output of the integrator in the integral path has a limiter at the output. What I'm confused about is how one should set these limits. Through experimentation with my program, I found that these limits will limit that amount of frequency deviation you allow in the output frequency signal \(\omega\). This in turn affects the speed of the response for the controller when the phase of the input signal given undergoes a step change. The more frequency deviation you allow (i.e. the larger your limits are) the faster the response of the controller (i.e. it will lock onto the phase of the signal faster). However, as a trade off for faster controller response, one observes more deviation in the frequency signal \(\omega\). Is there a way I can do some analysis to robustly determine how these limits affect the performance of the controller? Some guidance is all I'm asking for.

Thanks for all your help!