Simple Pseudo Random Number Generator with complete sequence

Thread Starter

Fra93

Joined Apr 22, 2020
5
I would like to present a personal invention of mine.

It is a circuit that can produce a pseudo-random sequence with a period of 2^n numbers, where n is the numbers of registers.
The general and low resource approach to produce a pseudo-random sequence in hardware is to use Fibonacci or Galois linear-feedback shift register (LFSR) but the period of the generated random sequence is limited to 2^n - 1 numbers.

Furthermore, with this new methodology there are more circuit types that produce a complete sequence, therefore, it is more resistant to mathematical attacks.

Here it is a link to the blog post:
Mod: Deleted Link.

Here to links to the code if someone wants to try it out:

I will post in the future the circuit with multiple bit lengths ( from 3 to 16 bits ).
Any feedback is really appreciated.

Mod: Please post the actual Code and other information to this Thread.
 
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Thread Starter

Fra93

Joined Apr 22, 2020
5
The main advantages are:
  • The produced sequence it is one number longer, and therefore complete.
  • The number of minimal polinomials for a given bit length in LFSR is smaller than the number of possible xor gate connection permutations in the parallel plane. Therefore, more mathematically secure.
  • You can optimize the transfer function reducing the number of bit shifts in the sequence.

I give concrete examples of all those points in my personal fdblog. With related code examples.

The circuit can be implemented in whatever programming language or hardware description language.
Probably I can give a C code example ( 16 bits ) in the future, like the Wikipedia page for LFSR.
 
Last edited:

Thread Starter

Fra93

Joined Apr 22, 2020
5
I have no problems in sharing the code.
I want it to reach as many people as possible.

Attached you can find what I already done. But many updates will come.

If there are better methods for sharing the code please let me know.
 

Attachments

jpanhalt

Joined Jan 18, 2008
9,347
You can simply post your code here as text. If you use code tags, e.g., [code] <insert code> [/code]
you can post inline.

I doubt few people will wade though a zipped file with links to your blog.
 

Thread Starter

Fra93

Joined Apr 22, 2020
5
I just downloaded all the project I have to gitlab as a zip file.

I want to point out that links to things I intend to maintain ( the RTL project as well as the blog ) with news related to the topic might be useful for somebody.

I post the RTL code as you suggest below.

Code:
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module dff
(
   input d,
   input ck,
   input rst,
   output q
 
);
    reg state;
 
    assign q = state;
 
    always @ (posedge ck or posedge rst )
    begin
        if (rst)
            state <= 'h0;
        else
            state <= d;
    end
 
endmodule

module nlprg8 (
  input ck,
  input rst,
  output o0,
  output o1,
  output o2,
  output o3,
  output o4,
  output o5,
  output o6,
  output o7
);
  wire s0;
  wire o0_temp;
  wire s1;
  wire o2_temp;
  wire s2;
  wire o1_temp;
  wire s3;
  wire o3_temp;
  wire o4_temp;
  wire o5_temp;
  wire o6_temp;
  wire o7_temp;
 
  dff dff0 (
    .d( s0 ),
    .ck( ck ),
    .rst( rst ),
    .q( o0_temp )
  );
 
  dff dff1 (
    .d( s1 ),
    .ck( ck ),
    .rst( rst ),
    .q( o2_temp )
  );
 
  dff dff2 (
    .d( s2 ),
    .ck( ck ),
    .rst( rst ),
    .q( o1_temp )
  );
 
  dff dff3 (
    .d( s3 ),
    .ck( ck ),
    .rst( rst ),
    .q( o3_temp )
  );
 
  dff dff4 (
    .d( o4_temp ),
    .ck( ck ),
    .rst( rst ),
    .q( o5_temp )
  );
 
  dff dff5 (
    .d( o3_temp ),
    .ck( ck ),
    .rst( rst ),
    .q( o4_temp )
  );
 
  dff dff6 (
    .d( o5_temp ),
    .ck( ck ),
    .rst( rst ),
    .q( o6_temp )
  );
 
  dff dff7 (
    .d( o6_temp ),
    .ck( ck ),
    .rst( rst ),
    .q( o7_temp )
  );
 
  assign s0 = (~ (o6_temp ^ o7_temp) ^ o3_temp);
  assign s1 = ~ (~ (o3_temp ^ o4_temp) ^ o1_temp);
  assign s2 = ~ (~ (o5_temp ^ o6_temp) ^ o0_temp);
  assign s3 = ((o5_temp ^ o2_temp) ^ (~ (o1_temp | o0_temp) & (((o7_temp & o6_temp) & (o5_temp & o4_temp)) & o3_temp)));
  assign o0 = o0_temp;
  assign o1 = o1_temp;
  assign o2 = o2_temp;
  assign o3 = o3_temp;
  assign o4 = o4_temp;
  assign o5 = o5_temp;
  assign o6 = o6_temp;
  assign o7 = o7_temp;
 
endmodule
 
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